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| CXD3048R CD Digital Signal Processor with Built-in Digital Servo + Shock-proof Memory Controller + Digital High & Bass Boost Description The CXD3048R is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, high & bass boost, shock-proof memory controller, 1-bit DAC and analog low-pass filter. Features * All digital signal processing during playback is performed with a single chip * Highly integrated mounting possible due to a built-in RAM Digital Signal Processor (DSP) Block * Supports CAV (Constant Angular Velocity) playback * Frame jitter free * 0.5x to 4x speed continuous playback possible * Allows relative rotational velocity readout * Wide capture range playback mode * Spindle rotational velocity following method * Supports 1x to 4x speed playback * Supports variable pitch playback * The bit clock, which strobes the EFM signal, is generated by the digital PLL. * EFM data demodulation * Enhanced EFM frame sync signal protection * Refined super strategy-based powerful error correction C1: double correction, C2: quadruple correction Supported during 4x speed playback * Noise reduction during track jumps * Auto zero-cross mute * Subcode demodulation and subcode-Q data error detection * Digital spindle servo * 16-bit traverse counter * Asymmetry correction circuit * CPU interface on serial bus * Error correction monitor signal, etc. output from a new CPU interface * Servo auto sequencer * Fine search performs track jumps with high accuracy * Digital audio interface outputs * Digital level meter, peak meter * Bilingual compatible * VCO control mode * CD TEXT data demodulation * Digital Out can be generated from the audio serial input. (also supported after shock-proof and digital bass boost processing, subcode-Q addition function) Digital Servo (DSSP) Block * Microcomputer software-based flexible servo control * Offset cancel function for servo error signal * Auto gain control function for servo loop * E:F balance, focus bias adjustment functions * Surf jump function supporting micro two-axis * Tracking filter: 6 stages Focus filter: 5 stages Shock-proof Memory Controller Block * Supports an external 4M-bit/16M-bit DRAM * Time axis-based data linking * ADPCM compression method (uncompressed/4 bits/ 6 bits/8 bits) 120 pin LQFP (Plastic) Digital Filter, DAC and Analog Low-pass Filter Blocks * Digital dynamic bass boost and high boost Bass Boost: 4th-order IIR 24dB/Oct +10dB/+14dB/+18dB/+22dB High Boost: Second-order IIR 12dB/Oct +4dB/+6dB/+8dB/+10dB * Independent turnover frequency selection possible Bass Boost: 125Hz/160Hz/200Hz High Boost: 5kHz/7kHz * Digital dynamics (compressor) Volume increased by +5dB at low level * 8x oversampling digital filter (attenuation: 61dB, ripple within band: 0.0075dB) * Digital signal output possible after boost * Serial data format selectable from (output) 20 bits/ 18 bits/16 bits (rearward truncation, MSB first) * Digital attenuation: - , -60 to +6dB, 2048 steps (linear) * Soft mute * Digital de-emphasis * High-cut filter Applications CD players Structure Silicon gate CMOS IC Absolute Maximum Ratings * Supply voltage VDD, AVDD Vss - 0.5 to +3.5 V * Input voltage VI Vss - 0.3 to VDD + 0.3 V * Output voltage VO Vss - 0.3 to VDD + 0.3 V * Storage temperature Tstg -55 to +150 C * Supply voltage difference AVSS - VSS -0.3 to +0.3 V AVDD - VDD -0.3 to +0.3V (AVDD < 1.7V) AVDD - VDD -0.3 to +1.0V (AVDD = 1.7 to 2.7V) Recommended Operating Conditions * Supply voltage VDD, AVDD0, 3, XVDD 1.7 to 2.7 VDD to 2.7 AVDD1, 2, DVDD * Operating temperature Topr -20 to +75 I/O Pin Capacitance * Input capacitance CI * Output capacitance CO Note) Measurement conditions 7 (max.) 7 (max.) VDD = VI = 0V fM = 1MHz V V C pF pF Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E02653A37 CXD3048R Block Diagram EMPH VPCO WFCK WDCK XUGF C2PO XTAO XTSL VCTL XTAI GFS TEST1 to 4 TES1 TEST XRST Clock Generator RFAC ASYI ASYO BIAS XPCK FILO FILI PCO CLTV MDP PWMI Digital CLV Shock-proof Memory Controller + Compression/ Expansion Digital PLL Sub Code Processor 32K RAM Asymmetry Corrector EFM demodulator Error Corrector D/A Interface Selector LRCK BCK PCMD Digital OUT DOUT A0 to A11 D0 to D3 XEMP XWIH XQOK XRAS XWE XCAS XWRE XSOE SENS DATA XLAT CLOK SCOR SBSO EXCK SQSO SQCK Signal Processor Block Memory Controller, Bass Boost Block CPU Interface Servo Auto Sequencer DAC XRDE SYSM LRMU LRCKI BCKI PCMDI HPL HPR LPF AOUT1 VREFL LPF AOUT2 VREFR Servo Block SERVO Interface SCLK COUT SSTP ATSK MIRR DFCT FOK PWM GENERATOR FOCUS PWM GENERATOR TRACKING PWM GENERATOR SLED PWM GENERATOR FFDR FRDR TFDR TRDR SFDR SRDR RFDC CE TE SE FE VC IGEN OPAmp Analog SW A/D Converter MIRR DFCT FOK SERVO DSP FOCUS SERVO TRACKING SERVO SLED SERVO -2- CXD3048R Pin Configuration AVDD0 AVDD3 VPCO COUT DOUT DFCT ATSK VDD1 PCO FOK LRMU 60 VSS1 59 TEST 58 TES1 57 AVDD2 56 AOUT2 55 VREFR 54 AVSS2 53 AVSS1 52 VREFL 51 AOUT1 50 AVDD1 49 XVSS 48 XTAO 47 XTAI 46 XVDD 45 HVDD 44 HPR 43 HPL 42 HVSS 41 XTSL 40 EXCK 39 SBSO 38 XWIH 37 XEMP 36 SQSO 35 SCLK 34 SQCK 33 VSS0 32 R4M 31 XWRE AVSS0 AVSS3 XUGF RFDC XPCK C2PO RFAC ASYO VCTL 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 SE 91 FE 92 VC 93 VSS2 94 FRDR 95 FFDR 96 TRDR 97 TFDR 98 SRDR 99 SFDR 100 SSTP 101 MDS 102 MDP 103 C176 104 VDD2 105 LRCK 106 LRCKI 107 PCMD 108 PCMDI 109 BCK 110 BCKI 111 DVDD 112 A3 113 A2 114 A1 115 A0 116 A10 117 A11 118 TEST3 119 TEST4 120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 XRAS FILI XRDE XWE CLOK D1 A6 TEST1 DATA DVSS A5 TEST2 SENS A4 VDD0 XCAS XLAT WFCK XSOE SYSM D0 A9 MIRR CLTV IGEN BIAS ASYI FILO GFS CE TE WDCK D3 A8 SCOR D2 A7 XRST PWMI -3- XQOK CXD3048R Pin Description Power Pin supply No. 1 2 3 4 5 6 7 8 9 DRAM 10 I/F 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Digital 25 26 27 28 29 30 31 Symbol XRAS XWE D1 D0 D3 D2 TEST1 TEST2 XCAS WFCK A9 A8 A7 DVSS A6 A5 A4 XRDE VDD0 CLOK DATA SENS XLAT XSOE SYSM WDCK SCOR XRST PWMI XQOK XWRE I/O Value O O 1, 0 1, 0 Description DRAM row address strobe signal. DRAM data input enable signal. DRAM data bus 1. DRAM data bus 0. DRAM data bus 3. DRAM data bus 2. Test pin. Do not connect. Test pin. Do not connect. 1, 0 1, 0 1, 0 1, 0 1, 0 -- 1, 0 1, 0 1, 0 DRAM column address strobe signal. WFCK output. XOE is output by switching with the command. DRAM address 9. DRAM address 8. DRAM address 7. DRAM interface GND. DRAM address 6. DRAM address 5. DRAM address 4. DRAM readout enable signal input. XRDE monitor is output by switching with the command. Digital power supply. Serial data transfer clock input from CPU. SQSO and SENS readout clocks are output by switching with the command. Serial data input from CPU. SENS output to CPU. SQSO data is output by switching with the command. Latch input from CPU. The serial data is latched at the falling edge. XLAT which is low for 6s or more is enabled. Clock input mode switching from CPU. Valid when $A4 ENXSOE = 1. Mute input. Muted when high. 1, 0 1, 0 Word clock output f = 2Fs. GRSCOR is output by switching with the command. High output when the subcode sync is detected. SCOR, which is interpolated in the IC, is output by switching with the command. System reset. Reset when low. Spindle motor external control input. Subcode Q OK input. XQOK monitor is output by switching with the command. DRAM write enable signal input. XWRE monitor is output by switching with the command. -4- I/O 1, 0 I/O 1, 0 I/O 1, 0 I/O 1, 0 O O O O O O O -- O O O I/O 1, 0 -- I I O 1, Z, 0 I I I O O I I I/O 1, 0 I/O 1, 0 -- CXD3048R Power Pin supply No. 32 33 34 35 36 Digital 37 38 39 40 41 42 43 H/P 44 45 46 47 X'tal 48 49 50 Lch 51 52 53 54 55 Rch 56 57 58 59 60 Digital 61 62 63 64 65 Symbol R4M Vss0 SQCK SCLK SQSO XEMP XWIH SBSO EXCK XTSL HVSS HPL HPR HVDD XVDD XTAI XTAO XVSS AVDD1 AOUT1 VREFL AVSS1 AVSS2 VREFR AOUT2 AVDD2 TES1 TEST VSS1 LRMU DOUT ATSK DFCT FOK I/O Value O -- I I O O O O I I -- O O -- -- 1, 0 1, 0 -- 1, 0 1, 0 1, 0 1, 0 1, 0 -- Description Microcomputer clock output. R8M and C4M are output by switching with the command. Digital GND. SQSO readout clock input. SENS serial data readout clock input. Subcode Q 80-bit and PCM peak and level data output. CD TEXT data output. DRAM readout prohibited signal. Write to DRAM prohibited signal. Subcode P to W serial output. SBSO readout clock input. Crystal selection input. Low when the crystal is 16.9344MHz; high when the crystal is 33.8688MHz. Headphone GND. Lch headphone PDM output. Rch headphone PDM output. Headphone power supply. Master clock power supply. Crystal oscillation circuit input. The master clock is externally input from this pin. Crystal oscillation circuit output. Master clock GND. I O -- -- Analog power supply. O Analog Lch analog output. O Analog Lch reference voltage. -- -- -- -- Analog GND. Analog GND. O Analog Rch reference voltage. O Analog Rch analog output. -- I I -- O O -- 1, 0 1, 0 -- Analog power supply. Test pin. Normally GND. Test pin. Normally GND. Digital GND. OR signal output of Lch, Rch "0" detection flag (AND output) and SYSM. Only "0" detection flag is output by switching with the command. Digital Out output. Anti-shock input/output. Defect signal input/output. Focus OK signal input/output. -5- I/O 1, 0 I/O 1, 0 I/O 1, 0 CXD3048R Power Pin supply No. 66 67 68 Digital 69 70 71 72 73 74 75 76 77 78 ASYM 79 80 81 82 83 84 85 86 87 88 A/D 89 90 91 92 93 94 95 96 Digital 97 98 99 Symbol MIRR COUT C2PO GFS XUGF XPCK VDD1 PCO FILI FILO CLTV VCTL VPCO AVSS3 ASYO ASYI BIAS AVDD3 RFAC AVDD0 IGEN AVSS0 RFDC CE TE SE FE VC VSS2 FRDR FFDR TRDR TFDR SRDR I/O Value I/O 1, 0 I/O 1, 0 O O O O -- I I I -- O I I -- I -- I -- I I I I I I -- O O O O O O -- 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 -- -- -- -- 1, 0 1, 0 1, 0 1, 0 1, 0 -- Mirror signal input/output. Description Track number count signal input/output. SCOR is output by switching with the command. C2PO output. MNT3 and GTOP are output by switching with the command. GFS output. MNT2 and XROF are output by switching with the command. XUGF output. MNT0, RFCK, C4M and QRCVD are output by switching with the command. XPCK output. MNT1, FSTO and GTOP are output by switching with the command. Digital power supply. Master PLL filter input. Multiplier VCO1 control voltage input. Wide-band EFM PLL VCO2 control voltage input. Analog GND. EFM full-swing output (low = Vss, high = VDD). Asymmetry comparator voltage input. Asymmetry circuit constant current input. Analog power supply. EFM signal input. Analog power supply. Operational amplifier constant current input. Analog GND. RF signal input. Center servo analog input or E input. Tracking error signal input or F input. Sled error signal input or B input. Focus error signal input or A input. Center voltage input. Digital GND. Focus drive output. Focus drive output. Tracking drive output. Tracking drive output. Sled drive output. Sled drive output. -6- O 1, Z, 0 Master PLL charge pump output. O Analog Master PLL (slave = digital PLL) filter output. O 1, Z, 0 Wide-band EFM PLL charge pump output. 100 SFDR CXD3048R Power Pin supply No. Symbol I/O Value I Description Disc innermost detection signal input. 101 SSTP 102 MDS Digital 103 MDP 104 C176 105 VDD2 106 LRCK 107 LRCKI 108 PCMD 109 PCMDI 110 BCK 111 BCKI 112 DVDD DRAM 113 A3 I/F 114 A2 115 A1 116 A0 117 A10 118 A11 119 TEST3 120 TEST4 O 1, Z, 0 Spindle drive output. O 1, Z, 0 Spindle motor servo control output. O -- O I O I O I -- O O O O O -- 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 -- 1, 0 176.4kHz output. 88.2kHz for quasi-double speed setting. Low output when XRST = low. Digital power supply. D/A interface. LR clock output f = Fs. D/A interface. LR clock input. D/A interface. Serial data output. (two's complement, MSB first) D/A interface. Serial data input. (two's complement, MSB first) D/A interface. Bit clock output. D/A interface. Bit clock input. DRAM interface power supply. DRAM address 3. DRAM address 2. DRAM address 1. DRAM address 0. DRAM address 10. DRAM address 11. Write prohibition factor is input by switching with the command. Test pin. Do not connect. Test pin. Do not connect. I/O 1, 0 O O Notes) * PCMD is a MSB first, two's complement output. * GTOP is used to monitor the frame sync protection status. (High: sync protection window released.) * XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync protection. * XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide. * The GFS signal goes high when the frame sync and the insertion protection timing match. * RFCK is derived from the crystal accuracy, and has a cycle of 136s. * C2PO represents the data error status. * XROF is generated when the 32K RAM exceeds the 28 frame jitter margin. * C4M is a 4.2336MHz output that changes in CAV-W mode and variable pitch mode. * R8M is the 8.4672MHz output. * FSTO is the 2/3 frequency-division output of the XTAI pin. * SOUT is the serial data output inside the servo block. * SOCK is the serial data readout clock output inside the servo block. * XOLT is the serial data latch output inside the servo block. -7- CXD3048R Monitor Pin Output Combinations Command bit MONSEL SRO1 0 0 0 0 0 1 0 0 0 0 1 -- MTSL1 MTSL0 0 0 1 1 0 -- 0 1 0 1 0 -- XUGF MNT0 RFCK C4M SOUT QRCVD XPCK MNT1 XPCK FSTO SOCK GTOP Output data GFS MNT2 XROF GFS XOLT GFS C2PO MNT3 GTOP C2PO C2PO C2PO COUT COUT COUT COUT COUT SCOR MIRR MIRR MIRR MIRR MIRR -- --: don't care -8- CXD3048R Electrical Characteristics 1. DC Characteristics (VDD1 = 2.5 0.2V, VDD2 (logic) = 1.8 0.1V, DVSS = VSS = 0V, Topr = -20 to +75C) Conditions VIH VIL Vt+ Vt- Vt+ - Vt- IOH = -4mA IOL = 4mA VIN = VSS or VDD VIN = VSS or VDD -10 -10 2.0 0.4 10 10 VOL II (1) II (2) Schmitt input 0.4 V A A 12, 13 15 13 1.7 0.7 V 14 Min. 1.7 0.7 Typ. Max. Unit V Applicable pins 13, 15 Item Input voltage High level input voltage (1) Low level input voltage High level input voltage Input voltage Low level input voltage (2) Hysteresis Output voltage High level output voltage VOH Low level output voltage Input leak current (1) Input leak current (2) (VDD = AVDD = 2.5 0.2V, Vss = AVss = 0V, Topr = -20 to +75C) Item Input voltage (1) Input voltage (2) Input voltage (3) High level input voltage Low level input voltage Input voltage High level input voltage Low level input voltage Hysteresis Output voltage (1) Output voltage (2) Output voltage (3) VIH (1) VIL (1) VIN (2) Vt+ Vt- Vt+ - Vt- 2.0 0.4 2.0 0.4 VDD 0.4 10 10 40 10 0 -10 -10 -40 -10 VOL (1) IOL = 4mA VOL (2) IOL = 2mA VOL (3) IOL = 0.36mA II (1) II (2) II (3) IOZ VIN = VSS or VDD VIN = VSS or VDD VIN = 0.25VDD to 0.75VDD VO = VSS or VDD -9- Schmitt input 0.4 V V V A A A A 2, 8, 10, 15 9 11 1, 3, 5, 6 2, 4 7 10 Analog input VSS 1.7 0.7 V 5 Conditions Min. 1.7 0.7 VDD Typ. Max. Unit V V Applicable pins 1, 2, 3, 4 6, 7 High level output voltage VOH (1) IOH = -4mA Low level output voltage Low level output voltage Low level output voltage High level output voltage VOH (2) IOH = -2mA High level output voltage VOH (3) IOH = -0.28mA VDD - 0.5 Input leak current (1) Input leak current (2) Input leak current (3) Tri-state output leak current (when high impedance) CXD3048R (VDD = AVDD = 1.8 0.1V, VSS = AVSS = 0V, Topr = -20 to +75C) Item Input voltage (1) Input voltage (2) Input voltage (3) High level input voltage Low level input voltage Input voltage High level input voltage Low level input voltage Hysteresis Output voltage (1) Output voltage (2) Output voltage (3) VIH (1) VIL (1) VIN (2) Vt+ Vt- Vt+ - Vt- VDD - 0.4 0 VDD - 0.4 0 0 -10 -10 -40 -10 VOL (1) IOL = 2.4mA VOL (2) IOL = 1.4mA VOL (3) IOL = 0.36mA II (1) II (2) II (3) IOZ VIN = VSS or VDD VIN = VSS or VDD VIN = 0.25VDD to 0.75VDD VO = VSS or VDD Schmitt input 0.4 VDD 0.4 VDD 0.4 VDD 0.4 10 10 40 10 V V V 2, 8, 10, 16 9 11 Analog input VSS 0.65VDD 0.35VDD V 5 Conditions Min. 0.65VDD 0.35VDD VDD Typ. Max. Unit V V Applicable pins 1, 2, 3, 4 6, 7 High level output voltage VOH (1) IOH = -2.4mA Low level output voltage Low level output voltage Low level output voltage High level output voltage VOH (2) IOH = -1.4mA High level output voltage VOH (3) IOH = -0.28mA VDD - 0.5 Input leak current (1) Input leak current (2) Input leak current (3) Tri-state output leak current (when high impedance) 1, 3, A 5, 6 A 2, 4 A 7 A 10 Applicable pins 1 TEST, TES1 2 COUT, MIRR, DFCT, FOK, XQOK, XWRE, ATSK 3 SYSM, DATA, XSOE, XTSL 4 SSTP, PWMI 5 SQCK, EXCK, XRST, CLOK, SCLK, XLAT 6 VCTL, FILI, CLTV, ASYI, IGEN, BIAS 7 RFDC, CE, TE, SE, FE, VC 8 XEMP, XWIH, SQSO, SBSO, XUGF, XPCK, GFS, C2PO, SCOR, WDCK, SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, ASYO, DOUT, C176 9 R4M 10 SENS, MDP, VPCO, PCO, MDS 11 FILO 12 A0 to A10, XRAS, XCAS, XWE, WFCK, LRCK, BCK, PCMD 13 D0 to D3, XRDE, A11 14 LRCKI, BCKI 15 PCMDI 16 HPL, HPR - 10 - CXD3048R 2. AC Characteristics (1) XTAI pin (a) When using self-excited oscillation (VDD = AVDD = 1.8 0.1V and 2.5 0.2V, Vss = AVss = 0V, Topr = -20 to +75C) Item Oscillation frequency Symbol fMAX Min. 7 Typ. Max. 34 Unit MHz (b) When inputting pulses to XTAI pin (VDD = AVDD = 1.8 0.1V and 2.5 0.2V, Vss = AVss = 0V, Topr = -20 to +75C) Item High level pulse width Low level pulse width Pulse cycle Input high level Input low level Rise time, fall time Symbol Min. 13 13 26 0.7VDD 0.2VDD 10 Typ. Max. 500 500 1000 Unit ns ns ns V V ns tWHX tWLX tCX VIHX VILX tR, tF tCX tWHX tWLX VIHX VIHX x 0.9 XTAI VDD/2 VIHX x 0.1 VILX tR tF Note) When the pulse is input to the XTAI pin, be sure to input it via the capacitor. - 11 - CXD3048R (2) CLOK, DATA, XLAT, SQCK and EXCK pins (VDD = AVDD = 1.8 0.1V and 2.5 0.2V, VSS = AVSS = 0V, Topr = -20 to +75C) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency EXCK SQCK pulse width COUT frequency (during input) COUT pulse width (during input) Symbol fCK Min. 750 300 300 300 750 0.65 750 65 7.5 30000 Typ. Max. 0.65 30000 Unit MHz ns ns ns ns ns MHz ns kHz s tWCK tSU tH tD tWL fT tWT fT tWT Only when $44 and $45 are executed. 1/fCK tWCK tWCK CLOK DATA tWSC XLAT EXCK SQCK COUT tWT 1/fT SBSO SQSO tSU tH tWT tSU tH tD tWL (3) R4M pin (when $A4X CKOUTSL2 = CKOUTSL1 = 0) (VDD = AVDD = 1.8 0.1V and 2.5 0.2V, VSS = AVSS = 0V, Topr = -20 to +75C) Item Output frequency Output duty Output amplitude Symbol fOUT DOUT VOUT Min. Typ. 4.2336 50 VDD Max. Unit MHz % V - 12 - CXD3048R (4) SCLK pin XLAT tDLS tSPW SCLK 1/fSCLK Serial Read Out Data (SENS) ... MSB ... LSB (VDD = AVDD = 1.8 0.1V and 2.5 0.2V, VSS = AVSS = 0V, Topr = -20 to +75C) Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK Min. 31.3 15 Typ. Max. 16 Unit MHz ns s tSPW tDLS (5) COUT, MIRR and DFCT pins Operating frequency (VDD = AVDD = 1.8 0.1V and 2.5 0.2V, VSS = AVSS = 0V, Topr = -20 to +75C) Item COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency Symbol fCOUT fMIRR fDFCTH Min. 40 40 5 Typ. Max. Unit kHz kHz kHz Conditions 1 2 3 1 When using a high-speed traverse TZC. 2 B A When the RF signal continuously satisfies the following conditions during the above traverse. * A = 0.11VDD to 0.23VDD * B 25% A+B 3 During complete RF signal omission. When settings related to DFCT signal generation are Typ. - 13 - CXD3048R 1-bit DAC and LPF Block Analog Characteristics Item Total harmonic distortion Symbol THD Conditions 1kHz sine wave, 0dB data, 20kHz LPF 1kHz sine wave, 0dB data, AMUT OFF (Using A-weighting filter 20kHz LPF) (VDD = AVDD = 2.6V, VSS = AVSS = 0V, Ta = +25C) Crystal 384Fs 768Fs 384Fs 768Fs 92 92 Min. Typ. 0.009 0.009 94 94 Max. 0.016 0.016 Unit % Signal-to-noise S/N ratio dB Fs = 44.1kHz in all cases. The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below. 100 AOUT1 (2) 22F Audio Analyzer 2200pF 100k VREFL (R) 1F LPF external circuit diagram ($A560C400 PDMSEL = 1) 768Fs/384Fs Rch DATA TEST DISC RF CXD3048R Lch A Audio Analyzer B Block diagram of analog characteristics measurement (VDD = AVDD = 2.6V, VSS = AVSS = 0V, Ta = +25C) Item Output voltage Load resistance VREF pin capacitance Symbol VOUT RL CVREF Min. 640 10 1 Typ. 658 Max. Unit mVrms k F Applicable pins 1 1 2 Measurement is conducted for the above circuit diagrams with the sine wave output of 1kHz and 0dB. Applicable pins 1 AOUT1, AOUT2 2 VREFL, VREFR - 14 - CXD3048R Contents [1] CPU Interface 1-1. CPU Interface Timing ...................................................................................................................... 1-2. CPU Interface Command Table ...................................................................................................... 1-3. CPU Command Presets ................................................................................................................. 1-4. Description of SENS Signals .......................................................................................................... 1-5. Description of Commands .............................................................................................................. 16 16 32 43 45 [2] Subcode Interface 2-1. P to W Subcode Readout ............................................................................................................. 101 2-2. 80-bit Subcode-Q Readout ........................................................................................................... 101 [3] Description of Modes 3-1. CLV-N Mode .................................................................................................................................. 3-2. CLV-W Mode ................................................................................................................................. 3-3. CAV-W Mode ................................................................................................................................. 3-4. VCO-C Mode ................................................................................................................................ [4] Description of Other Functions 4-1. Channel Clock Recovery by Digital PLL Circuit ........................................................................... 4-2. Frame Sync Protection ................................................................................................................. 4-3. Error Correction ............................................................................................................................ 4-4. DA Interface .................................................................................................................................. 4-5. Digital Out ..................................................................................................................................... 4-6. Servo Auto Sequence ................................................................................................................... 4-7. Digital CLV .................................................................................................................................... 4-8. CD-DSP Block Playback Speed ................................................................................................... 4-9. Description of DAC Block and Shock-proof Memory Controller Block Circuits ............................ 4-10. DAC Block Input Timing ................................................................................................................ 4-11. Description of DAC Block Functions ............................................................................................. 4-12. LPF Block...................................................................................................................................... 4-13. Description of Shock-proof Memory Controller Block Functions .................................................. 4-14. CPU to DRAM Access Function ................................................................................................... 4-15. Asymmetry Correction .................................................................................................................. 4-16. CD TEXT Data Demodulation ....................................................................................................... [5] Description of Servo Signal Processing System Functions and Commands 5-1. General Description of Servo Signal Processing System ............................................................ 5-2. Digital Servo Block Master Clock (MCK) ...................................................................................... 5-3. DC Offset Cancel [AVRG Measurement and Compensation] ...................................................... 5-4. E:F Balance Adjustment Function ................................................................................................ 5-5. FCS Bias Adjustment Function ..................................................................................................... 5-6. AGCNTL Function ......................................................................................................................... 5-7. FCS Servo and FCS Search ........................................................................................................ 5-8. TRK and SLD Servo Control ........................................................................................................ 5-9. MIRR and DFCT Signal Generation ............................................................................................. 5-10. DFCT Countermeasure Circuit ..................................................................................................... 5-11. Anti-shock Circuit .......................................................................................................................... 5-12. Brake Circuit ................................................................................................................................. 5-13. COUT Signal ................................................................................................................................. 5-14. Serial Readout Circuit ................................................................................................................... 5-15. Writing to Coefficient RAM ........................................................................................................... 5-16. PWM Output ................................................................................................................................. 5-17. Servo Status Changes Produced by LOCK Signal ...................................................................... 5-18. Description of Commands and Data Sets .................................................................................... 5-19. List of Servo Filter Coefficients ..................................................................................................... 5-20. Filter Composition ......................................................................................................................... 5-21. TRACKING and FOCUS Frequency Response ........................................................................... 108 108 108 109 112 114 114 115 118 124 132 133 133 134 135 140 141 146 150 151 153 154 155 156 156 158 160 161 162 163 163 164 165 165 166 166 167 167 195 197 203 [6] Application Circuit .................................................................................................................................. 204 Explanation of abbreviations AVRG: Average AGCNTL: Auto gain control FCS: Focus TRK: Tracking SLD: Sled DFCT: Defect - 15 - CXD3048R [1] CPU Interface 1-1. CPU Interface Timing * CPU interface This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below. (See 2. AC Characteristics in Electrical Characteristics, for the details of the AC characteristics.) 750ns to 30s CLOK DATA D0 D1 D18 D19 D20 D21 D22 D23 750ns or more (6s or more when $AAX MLAT ON) Valid XLAT Registers * The internal registers are initialized by a reset when XRST = 0. 1-2. CPU Interface Command Table Total bit length for each register Register 0 to 2 3 4 to 6 7 8 9 A B C D E Total bit length 8 bits 8 to 24 bits 16 bits 20 bits 32 bits 32 bits 32 bits 28 bits 28 bits 28 bits 20 bits - 16 - Command Table ($0X to 1X) Register Address Command D23 to D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP ANTI SHOCK ON Data 1 Data 2 Data 3 Data 4 Data 5 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 FOCUS CONTROL 0000 0 -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 17 - 1 TRACKING CONTROL 0001 0 -- 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ANTI SHOCK OFF -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BRAKE ON -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BRAKE OFF TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 -- -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CXD3048R -- -- -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TRACKING GAIN UP FILTER SELECT 2 --: don't care Command Table ($2X to 3X) Register Address Command D23 to D20 D19 0 D18 0 D17 -- D16 -- D15 -- D14 -- D13 -- D12 -- D11 -- D10 -- D9 -- D8 -- D7 -- D6 -- D5 -- D4 -- D3 -- D2 -- D1 -- D0 -- TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF Data 1 Data 2 Data 3 Data 4 Data 5 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 2 TRACKING CONTROL 0010 -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE -- -- 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - 18 - Register Command 3 SELECT 0011 -- Address D23 to D20 D19 0 -- 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 1 D18 0 D17 0 D16 0 D15 -- Data 2 D14 -- D13 -- D12 -- D11 -- Data 3 D10 -- D9 -- D8 -- D7 -- Data 4 D6 -- D5 -- D4 -- D3 -- Data 5 D2 -- D1 -- D0 -- SLED KICK LEVEL (1 x basic value) (default) SLED KICK LEVEL (2 x basic value) SLED KICK LEVEL (3 x basic value) SLED KICK LEVEL (4 x basic value) --: don't care 0 0 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 1 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CXD3048R Command Table ($340X) Register Address 1 Command D23 to D20 D19 to D16 D15 to D12 D11 0 D10 0 D9 0 D8 0 D7 D6 D5 D4 D3 D2 D1 D0 KRAM DATA (K00) SLED INPUT GAIN KRAM DATA (K01) SLED LOW BOOST FILTER A-H KRAM DATA (K02) SLED LOW BOOST FILTER A-L KRAM DATA (K03) SLED LOW BOOST FILTER B-H KRAM DATA (K04) SLED LOW BOOST FILTER B-L KRAM DATA (K05) SLED OUTPUT GAIN KRAM DATA (K06) FOCUS INPUT GAIN KRAM DATA (K07) SLED AUTO GAIN KRAM DATA (K08) FOCUS HIGH CUT FILTER A KRAM DATA (K09) FOCUS HIGH CUT FILTER B KRAM DATA (K0A) FOCUS LOW BOOST FILTER A-H KRAM DATA (K0B) FOCUS LOW BOOST FILTER A-L KRAM DATA (K0C) FOCUS LOW BOOST FILTER B-H KRAM DATA (K0D) FOCUS LOW BOOST FILTER B-L KRAM DATA (K0E) FOCUS PHASE COMPENSATE FILTER A KRAM DATA (K0F) FOCUS DEFECT HOLD GAIN Address 2 Address 3 Address 4 Data 1 Data 2 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 - 19 - 3 SELECT 0011 0100 0000 0 1 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 CXD3048R 1 1 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 Command Table ($341X) Register Address 1 Command D23 to D20 D19 to D16 D15 to D12 D11 0 D10 0 D9 0 D8 0 D7 D6 D5 D4 D3 D2 D1 D0 KRAM DATA (K10) FOCUS PHASE COMPENSATE FILTER B KRAM DATA (K11) FOCUS OUTPUT GAIN KRAM DATA (K12) ANTI SHOCK INPUT GAIN KRAM DATA (K13) FOCUS AUTO GAIN KRAM DATA (K14) HPTZC / AUTO GAIN HIGH PASS FILTER A KRAM DATA (K15) HPTZC / AUTO GAIN HIGH PASS FILTER B KRAM DATA (K16) ANTI SHOCK HIGH PASS FILTER A KRAM DATA (K17) HPTZC / AUTO GAIN LOW PASS FILTER B KRAM DATA (K18) FIX KRAM DATA (K19) TRACKING INPUT GAIN KRAM DATA (K1A) TRACKING HIGH CUT FILTER A KRAM DATA (K1B) TRACKING HIGH CUT FILTER B KRAM DATA (K1C) TRACKING LOW BOOST FILTER A-H KRAM DATA (K1D) TRACKING LOW BOOST FILTER A-L KRAM DATA (K1E) TRACKING LOW BOOST FILTER B-H KRAM DATA (K1F) TRACKING LOW BOOST FILTER B-L Address 2 Address 3 Address 4 Data 1 Data 2 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 - 20 - 3 SELECT 0011 0100 0001 0 1 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 CXD3048R 1 1 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 Command Table ($342X) Register Address 1 Command D23 to D20 D19 to D16 D15 to D12 D11 0 D10 0 D9 0 D8 0 D7 D6 D5 D4 D3 D2 D1 D0 KRAM DATA (K20) TRACKING PHASE COMPENSATE FILTER A KRAM DATA (K21) TRACKING PHASE COMPENSATE FILTER B KRAM DATA (K22) TRACKING OUTPUT GAIN KRAM DATA (K23) TRACKING AUTO GAIN KRAM DATA (K24) FOCUS GAIN DOWN HIGH CUT FILTER A KRAM DATA (K25) FOCUS GAIN DOWN HIGH CUT FILTER B KRAM DATA (K26) FOCUS GAIN DOWN LOW BOOST FILTER A-H KRAM DATA (K27) FOCUS GAIN DOWN LOW BOOST FILTER A-L KRAM DATA (K28) FOCUS GAIN DOWN LOW BOOST FILTER B-H KRAM DATA (K29) FOCUS GAIN DOWN LOW BOOST FILTER B-L KRAM DATA (K2A) FOCUS GAIN DOWN PHASE COMPENSATE FILTER A KRAM DATA (K2B) FOCUS GAIN DOWN DEFECT HOLD GAIN KRAM DATA (K2C) FOCUS GAIN DOWN PHASE COMPENSATE FILTER B KRAM DATA (K2D) FOCUS GAIN DOWN OUTPUT GAIN KRAM DATA (K2E) Not used KRAM DATA (K2F) Not used Address 2 Address 3 Address 4 Data 1 Data 2 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 - 21 - 3 SELECT 0011 0100 0010 0 1 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 CXD3048R 1 1 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 Command Table ($343X) Address 1 Address 2 Address 3 RegisCommand ter D23 to D20 D19 to D16 D15 to D12 D11 0 Address 4 D10 0 D9 0 D8 0 D7 Data 1 D6 D5 D4 D3 Data 2 D2 D1 D0 KRAM DATA (K30) SLED INPUT GAIN (when TGup2 is accessed with SFSK = 1) KRAM DATA (K31) ANTI SHOCK LOW PASS FILTER B KRAM DATA (K32) Not used KRAM DATA (K33) ANTI SHOCK HIGH PASS FILTER B-H KRAM DATA (K34) ANTI SHOCK HIGH PASS FILTER B-L KRAM DATA (K35) ANTI SHOCK FILTER COMPARATE GAIN KRAM DATA (K36) TRACKING GAIN UP2 HIGH CUT FILTER A KRAM DATA (K37) TRACKING GAIN UP2 HIGH CUT FILTER B KRAM DATA (K38) TRACKING GAIN UP2 LOW BOOST FILTER A-H KRAM DATA (K39) TRACKING GAIN UP2 LOW BOOST FILTER A-L KRAM DATA (K3A) TRACKING GAIN UP2 LOW BOOST FILTER B-H KRAM DATA (K3B) TRACKING GAIN UP2 LOW BOOST FILTER B-L KRAM DATA (K3C) TRACKING GAIN UP PHASE COMPENSATE FILTER A KRAM DATA (K3D) TRACKING GAIN UP PHASE COMPENSATE FILTER B KRAM DATA (K3E) TRACKING GAIN UP OUTPUT GAIN KRAM DATA (K3F) Not used KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 - 22 - 3 SELECT 0011 0100 0011 0 1 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 CXD3048R 1 1 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 Command Table ($344X) Address 1 Address 2 Address 3 RegisCommand ter D23 to D20 D19 to D16 D15 to D12 D11 0 Address 4 D10 0 D9 0 D8 0 D7 Data 1 D6 D5 D4 D3 Data 2 D2 D1 D0 KRAM DATA (K40) TRACKING HOLD FILTER INPUT GAIN KRAM DATA (K41) TRACKING HOLD FILTER A-H KRAM DATA (K42) TRACKING HOLD FILTER A-L KRAM DATA (K43) TRACKING HOLD FILTER B-H KRAM DATA (K44) TRACKING HOLD FILTER B-L KRAM DATA (K45) TRACKING HOLD FILTER OUTPUT GAIN KRAM DATA (K46) TRACKING HOLD INPUT GAIN (when TGup2 is accessed with THSK = 1) KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 0 1 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 - 23 - 3 SELECT 0011 0100 0100 0 1 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 KRAM DATA (K47) Not used KRAM DATA (K48) FOCUS HOLD FILTER INPUT GAIN KRAM DATA (K49) FOCUS HOLD FILTER A-H KRAM DATA (K4A) FOCUS HOLD FILTER A-L KRAM DATA (K4B) FOCUS HOLD FILTER B-H KRAM DATA (K4C) FOCUS HOLD FILTER B-L KRAM DATA (K4D) FOCUS HOLD FILTER OUTPUT GAIN KRAM DATA (K4E) Not used KRAM DATA (K4F) Not used 1 0 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 0 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 0 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 CXD3048R 1 1 1 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 1 1 1 1 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 Command Table ($348X to 3FX) Register Address 1 Command D23 to D20 D19 to D16 D15 1 D14 0 D13 0 D12 0 D11 D10 D9 D8 D7 0 D6 0 D5 0 D4 D3 D2 D1 0 D0 0 PGFS, PFOK, RFAC PGFS PGFS PFOK PFOK 1 0 1 0 Address 2 Address 3 Data 1 Data 2 Data 3 MRS MRT1 MRT0 1 0 1 0 A/D COPY EMPH CAT DOUT DOUT DOUT WIN DOUT SEL EN b8 EN1 DMUT WOD EN EN2 D SFBK SFBK 1 2 0 0 LB1 SN LB2 SN 0 LB2 SM 0 0 0 0 0 DOUT 1 0 1 1 0 0 0 Booster Surf Brake 1 1 0 0 THB FHB TLB1 FLB1 TLB2 ON ON ON ON ON IDF SL3 IDF SL2 IDF SL1 IDF SL0 0 HBST HBST LB1S LB1S LB2S LB2S Booster 1 0 1 0 1 0 0 0 LPDF INV DFCT 0 RFDC 3 SELECT 0011 0100 1 1 1 0 DF IDFT IDFT 1 0 SLS Data 2 Address 3 D15 D14 D13 D12 D11 1 D10 0 Data 1 D9 D8 D7 Data 3 D4 D3 D2 D1 D0 -- FCS Bias Limit D6 D5 - 24 - 1 1 1 1 FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 0 1 FB9 FB8 FB7 FB6 FB5 FB4 FB3 FB2 FB1 -- FCS Bias Data 0 0 TV9 TV8 TV7 TV6 TV5 TV4 TV3 TV2 TV1 TV0 Traverse Center Data --: don't care CXD3048R Command Table ($34FX to 3FX) cont. Address 1 RegisCommand ter D23 to D20 D19 0 Address 2 D18 1 D17 0 D16 1 D15 FT1 Data 1 D14 FT0 D13 FS5 D12 FS4 D11 FS3 Data 2 D10 FS2 D9 FS1 D8 FS0 D7 FTZ Data 3 D6 FG6 D5 D4 D3 Data 4 D2 D1 D0 FG0 FCS search, AGF FG5 FG4 FG3 FG2 FG1 0 1 1 0 TDZC DTZC TJ5 TJ4 TJ3 TJ2 TJ1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 TRK jump, AGT 0 1 1 1 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZC, AGC, SLD move 1 0 0 0 VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 DC measure, cancel 1 0 0 1 DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 0 0 0 0 0 0 0 Serial data readout FCS Bias, Gain, Surf jump / brake Gain 0 FBON FBSS FBUP FBV1 FBV0 FIF TJD0 FPS1 FPS0 TPS1 TPS0 SVDA SJHD INBK MTI0 ZC 0 UD FZC 0 0 0 0 0 0 0 0 1 3 SELECT 0011 1 0 1 0 1 0 0 0 FPG FPG TPG TPG S0 S1 S0 S1 0 0 0 0 - 25 - 0 0 1 0 0 0 0 0 0 0 FOCUS 1 1 1 1 1 1 1 1 0 0 0 SRQ1 SRQ0 0 0 ASYO 1 0 1 1 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT 0 0 0 Mirr, DFCT, FOK TZC, COUT, Bottom, MIRR SLD filter 1 1 0 0 COSS COTS CETZ CETF COT2 COT1 MOT2 0 BTS1 BTS0 MRC1 MRC0 0 0 0 0 1 1 0 1 SFID SFSK THID THSK ABEF TLD2 TLD1 TLD0 SDF6 SDF5 SDF4 SDF3 0 0 0 0 1 1 1 0 F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD 0 LKIN COIN MDFI MIRI XT1D Filter 1 1 1 1 0 AGG4 XT4D XT2D 0 DRR2 DRR1 DRR0 0 ASFG FTQ 1 SRO1 0 AGHF ASOT Clock, others CXD3048R Command Table ($34FX to 3FX) cont. Address 1 RegisCommand ter D23 to D20 D19 Address 2 D18 D17 D16 D15 1 3 SELECT 0011 1 1 1 1 1 0 0 1 FSUD FFS UP 0 1 0 0 FFS5 FFS4 FFS3 FFS2 FFS1 FFS0 FOCUS Address 3 D14 0 D13 0 D12 0 D11 Data 1 D10 D9 D8 D7 Data 2 D6 D5 D4 D3 Data 3 D2 D1 D0 SYG3 SYG2 SYG1 SYG0 FI FI FI FI FI FI FI FI System GAIN FZB3 FZB2 FZB1 FZB0 FZA3 FZA2 FZA1 FZA0 - 26 - CXD3048R Command Table ($4X to EX) Register 4 Address Command D3 Auto sequence Blind (A, E), Brake (B), Overflow (C, G) Sled KICK, BRAKE (D), KICK (F) Auto sequence (N) track jump count setting MODE specification Function specification 0 D2 1 D1 0 D0 0 D3 AS3 D2 AS2 D1 AS1 D0 AS0 D3 MT3 D2 MT2 D1 MT1 D0 MT0 D3 LSSL D2 0 D1 0 D0 0 D3 -- D2 -- D1 -- D0 -- Data 1 Data 2 Data 3 Data 4 5 0 1 0 1 TR3 TR2 TR1 TR0 0 0 0 0 0 0 0 0 -- -- -- -- 6 0 1 1 0 SD3 SD2 SD1 SD0 KF3 KF2 KF1 KF0 0 0 0 0 -- -- -- -- 7 0 1 1 1 32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 8 1 0 0 0 CDROM 1 DOUT DOUT WSEL Mute Mute-F DSPB ASEQ ON-OFF ON-OFF 1 VCO SEL2 BiliGL MAIN ASHS SOCT0 BiliGL SUB VCO SEL1 0 KSL3 KSL2 KSL1 KSL0 0 VCO1 CS0 0 0 0 - 27 - 9 1 0 0 1 FLFC 0 0 0 0 1 0 1 --: don't care CXD3048R Command Table ($4X to EX) cont. Register Address Command D3 Audio CTRL D2 D1 D0 D3 0 D2 0 D1 Mute D0 ATT D3 PCT1 D2 PCT2 D1 0 D0 SOC2 D3 0 D2 0 D1 0 D0 0 D3 0 D2 1 D1 0 D0 0 Data 1 Data 2 Data 3 Data 4 Signal select 0 1 0 0 RSL1 RSL0 0 0 DTSL1 DTSL0 MCSL1 MCSL0 0 SDSL2 SDSL1 SDSL0 0 0 1 ZMUTA SMUT AD10 AD9 AD8 BST CL AD7 AD6 PDM SEL AD5 AD4 0 Bass boost 0 1 0 1 1 1 PWDN ZDPL WOC DAC HiCut EMPH FILTER 1 OBIT1 OBIT0 BBST BBST Vdwn1 Vdwn0 1 0 0 BBON1 BBON0 HBON1 HBON0 BBSL1 BBSL0 HBSL1 HBSL0 COMP ON 1 1 1 0 0 0 0 0 0 0 - 28 - A Headphone 1 0 1 0 0 1 1 0 Shock-proof memory setting Shock-proof memory control DOUT subcode-Q setting 1 DRAM I/F 0 0 1 0 1 1 1 1 0 0 0 0 0 0 SMUT AD10 AD9 AD8 BST CL AD7 AD6 PDM SEL AD5 AD4 0 1 PWDN ZDPL XWOC DAC HiCut EMPH FILTER 1 1 0 1 0 BBON1 BBON0 HBON1 HBON0 BBSL1 BBSL0 HBSL1 HBSL0 COMP ON BBST BBST Vdwn1 Vdwn0 1 0 1 1 0 0 0 0 0 0 0 XOE SL GTOP NOLIM SPSL SL READ2 REFSEL REFON OUT XQOK XWRE CHECK WDCK COM XQOK XWRE XRDE XSOEO XSOEO2 ADDRST 0 SDTO OUT 0 MSL2 MSL1 MSL0 SubQA3 SubQA2 SubQA1 SubQA0 0 0 0 SubQD7 SubQD6 SubQD5 SubQD4 1 1 1 0 1 DRWR DRADR 0 DRD15 DRD14 DRD13 DRD12 CXD3048R 1 1 1 1 DADR19 DADR18 DADR17 DADR16 DADR15 DADR14 DADR13 DADR12 Command Table ($4X to EX) cont. Register Address Command D3 Compression setting EFM playability enhancement setting Sync expansion specification A Sleep setting Variable pitch setting Spindle servo setting B Traverse monitor counter setting Spindle servo coefficient setting CLV CTRL 1 0 1 0 1 1 0 1 ADCPS VARI ON SYG3 EA 2048 HCAV ERCNT LPF DSUB ASEQ DSP DSSP ASYM ESP PCOL SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP VARI USE SYG2 EA 1024 WTC C2PO SYG1 EA 512 SCSY (sub) SENS SEL3 SENS SENS SEL2 SEL1 SENS SEL0 0 MDS CTL 8 MDP UP 4 0 MDP CTL4 1 0 D2 D1 D0 D3 1 D2 0 D1 1 D0 0 D3 D2 D1 D0 0 D3 ADP WO 1 D2 0 D1 0 D0 0 D3 0 D2 GRSEL D1 0 D0 0 Data 1 Data 2 Data 3 Data 4 ADPON BITSL1 BITSL0 1 0 1 1 ARDTEN 1 1 1 0 1 0 0 0 1 0 1 1 0 0 AVW 0 SFP5 SFP4 SFP3 SFP2 SFP1 SFP0 0 0 0 0 1 1 1 0 1 1 1 1 MDP SYG0 MDP LPWR2 EA OUTSL1 OUTSL0 256 128 64 32 - 29 - 1 0 1 1 32768 16384 8192 4096 16 2 C 1 1 0 0 Gain Gain Gain Gain Gain Gain PCC1 MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0 0 TB TP Gain CLVS CM0 VP7 VP6 VP5 PCC0 SFP3 SFP2 SFP1 SFP0 SRP3 VP CTL1 Gain CAV1 SRP2 VP CTL0 Gain CAV0 SPR1 SRP0 D 1 1 0 1 VP4 VP3 VP2 VP1 VP0 0 0 INV VPCO E SPD mode 1 1 1 0 CM3 CM2 CM1 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON 0 CXD3048R Command Table ($4X to EX) cont. Register 8 Data 5 Command MODE specification Function specification AUDIO CTRL Address Data 1 Data 2 Data 3 Data 4 D3 1000 ERC4 D2 D1 D0 D3 D2 D1 D0 D3 0 D2 0 D1 OUTL2 D0 0 SCOR SCSY SOCT1 TXON TXOUT OUTL1 OUTL0 SEL 0 0 0 0 0 0 0 Data 6 Data 7 9 1001 00 0 DIV4 0 0 0 0 0 0 0 0 0 0 0 -- -- -- -- Signal select 0100 001 01 max max max max max max max max EN CKOUT CKOUT SLD XSOE SL2 SL1 BBIN C2PO7 C2PO6 C2PO5 C2PO4 C2PO3 C2PO2 C2PO1 C2PO0 AD3 AD2 AD1 AD0 setup 0 0 0 0 BBST Vup1 0 1 BBST Vup0 0 0 BBST Uth 0 0 BBST Lth PDM INV AD0 Bass boost 0101 10 110 - 30 - A 1010 Headphone 0110 Shock-proof memory setting DOUT subcode-Q setting 0111 1001 001 01 10 110 AD3 AD2 AD1 0 BBST Vup1 0 1 BBST Vup0 0 0 BBST Uth 0 0 BBST Lth PDM INV STA SEL XWI H2 XWI H1 SPSL COM WQR MON A11 SEL READ READ S1 S2 MON SEL ADDRST ADRMO SEL 0000 0 SubQD3 SubQD2 SubQD1 SubQD0 CXD3048R --: don't care Command Table ($4X to EX) cont. Register Data 5 Command Address Data 1 Data 2 Data 3 Data 4 D3 1110 DRAM I/F 1001 1111 Compression setting A 1010 EFM playability enhancement setting Sync expansion specification Spindle servo setting 1011 1 0 0 0 0 0 0 0 1 0 0 0 DADR11 DADR10 DADR9 DADR8 DADR7 DADR6 DADR5 DADR4 DADR3 DADR2 DADR1 DADR0 ADPCM ADPCM SEL MUTE D2 D1 D0 D3 D2 D1 D0 DRD4 D3 DRD3 D2 DRD2 D1 DRD1 D0 DRD0 Data 6 Data 7 DRD11 DRD10 DRD9 DRD8 DRD7 DRD6 DRD5 1010 0 0 0 ORMU 0 0 1100 REF SEL2 MDP CTL3 0 SLIM1 SLIM0 MDP CTL2 0 MDP CTL1 OV4 MDP CTL0 OV3 OV2 OV1 OV0 1111 - 31 - B Traverse monitor counter setting Spindle servo coefficient setting CLV CTRL 1011 MTSL1 MTSL0 ASYE MD2 0 0 C 1100 EDC7 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 -- -- -- -- D 1101 0 0 0 0 0 0 0 0 -- -- -- -- --: don't care CXD3048R 1-3. CPU Command Presets Command Preset Table ($0X to 34X) Register 0 Address Command D23 to D20 D19 FOCUS CONTROL TRACKING CONTROL TRACKING MODE Command 0000 0 D18 0 D17 0 D16 0 D15 -- D14 -- D13 -- D12 -- D11 -- D10 -- D9 -- D8 -- D7 -- D6 -- D5 -- D4 -- D3 -- D2 -- D1 -- D0 -- FOCUS SERVO OFF, 0V OUT TRACKING GAIN UP FILTER SELECT 1 TRACKING SERVO OFF SLED SERVO OFF Data 1 Data 2 Data 3 Data 4 Data 5 1 0001 0 0 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 Register 0010 0 0 0 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Address D23 to D20 D19 0011 0 D18 0 Data 1 D17 0 D16 0 D15 -- Data 2 D14 -- D13 -- D12 -- D11 -- Data 3 D10 -- D9 -- D8 -- D7 -- Data 4 D6 -- D5 -- D4 -- D3 -- Data 5 D2 -- D1 -- D0 -- SLED KICK LEVEL (1 x basic value) (default) - 32 - Address 1 3 SELECT D23 to D20 D19 0011 0 D18 1 D17 0 D16 0 D15 0 Address 2 D14 D13 D12 D11 Address 3 D10 D9 D8 D7 Data 1 D6 D5 D4 D3 Data 2 D2 D1 D0 KRAM DATA ($3400XX to $344FXX) --: don't care See "Coefficient ROM Preset Values Table" CXD3048R Command Preset Table ($348X to 34FX) Register Address 1 Command D23 to D20 D19 to D16 D15 1 D14 0 D13 0 D12 0 D11 0 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 PGFS, PFOK, RFAC Address 2 Address 3 Data 1 Data 2 Data 3 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 DOUT 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Booster Surf Brake 1 3 SELECT 0011 0100 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Booster 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 DFCT Address 3 D15 D14 D13 D12 D11 1 D10 0 Data 1 D9 0 D8 0 D7 0 Data 2 D6 0 D5 0 D4 0 D3 0 Data 3 D2 0 D1 0 D0 -- FCS Bias Limit - 33 - 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 -- FCS Bias Data 0 0 0 0 0 0 0 0 0 0 0 0 Traverse Center Data --: don't care CXD3048R Command Preset Table ($34FX to 3FX) cont. Register Address 1 Command D23 to D20 D19 0 D18 1 D17 0 D16 1 D15 0 D14 1 D13 0 D12 1 D11 1 D10 0 D9 0 D8 0 D7 0 D6 0 D5 1 D4 0 D3 1 D2 1 D1 0 D0 1 FCS search, AGF Address 2 Data 1 Data 2 Data 3 Data 4 0 1 1 0 0 0 0 0 1 1 1 0 0 0 1 0 1 1 1 0 TRK jump, AGT 0 1 1 1 0 1 0 1 0 0 0 0 1 0 1 1 0 0 1 0 FZC, AGC, SLD move 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DC measure, cancel 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Serial data read out FCS Bias, Gain, Surf jump / brake Gain 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - 34 - 1 3 SELECT 0011 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 FOCUS 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 ASYO 1 0 1 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 MIRR, DFCT, FOK TZC, COUT, Bottom, MIRR SLD filter 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Filter 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Clock, others CXD3048R Command Preset Table ($34FX to 3FX) cont. Register Address 1 Command D23 to D20 D19 D18 D17 D16 D15 1 3 SELECT 0011 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 FOCUS D14 0 D13 0 D12 0 D11 1 D10 0 D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 System GAIN Address 2 Address 3 Data 1 Data 2 Data 3 - 35 - CXD3048R Command Preset Table ($4X to EX) Register 4 Address Command D3 Auto sequence Blind (A, E), Brake (B), Overflow (C, G) Sled KICK, BRAKE (D), KICK (F) Auto sequence (N) track jump count setting MODE setting Function specification 0 D2 1 D1 0 D0 0 D3 0 D2 0 D1 0 D0 0 D3 0 D2 0 D1 0 D0 0 D3 0 D2 0 D1 0 D0 0 D3 -- D2 -- D1 -- D0 -- Data 1 Data 2 Data 3 Data 4 5 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 -- -- -- -- 6 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 -- -- -- -- 7 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 8 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 - 36 - 9 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 --: dun't care CXD3048R Command Preset Table ($4X to EX) cont. Register Address Command D3 Audio CTRL D2 D1 D0 D3 0 D2 0 D1 1 D0 1 D3 0 D2 0 D1 0 D0 0 D3 0 D2 0 D1 0 D0 0 D3 0 D2 1 D1 0 D0 0 Data 1 Data 2 Data 3 Data 4 Signal select 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 Bass boost 0 1 0 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 - 37 - A Headphone 1 0 1 0 0 1 1 0 Shock-proof memory setting Shock-proof memory control DOUT subcode-Q setting 1 DRAM I/F 0 0 1 0 1 1 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 CXD3048R 1 1 1 1 0 0 0 0 0 0 0 0 Command Preset Table ($4X to EX) cont. Register Address Command D3 Compression setting EFM playability enhancement setting Sync expansion specification A Sleep setting Variable pitch setting Spindle servo setting B Traverse monitor counter setting Spindle servo coefficient setting CLV CTRL 1 0 1 0 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 D2 D1 D0 D3 1 D2 0 D1 1 D0 0 D3 0 D2 0 D1 0 D0 0 D3 0 D2 0 D1 0 D0 0 D3 0 D2 0 D1 0 D0 0 Data 1 Data 2 Data 3 Data 4 1 0 1 1 0 1 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 - 38 - 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 C 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 D 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E SPD mode 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CXD3048R Command Preset Table ($4X to EX) cont. Register 8 Data 5 Command MODE specification Function specification AUDIO CTRL Address Data 1 Data 2 Data 3 Data 4 D3 1000 0 D2 0 D1 0 D0 0 D3 0 D2 0 D1 0 D0 0 D3 0 D2 0 D1 0 D0 0 Data 6 Data 7 9 1001 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -- -- -- -- Signal select 0100 001 01 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Bass boost 0101 10 110 001 01 0 0 0 0 - 39 - A 1010 Headphone 0110 Shock-proof memory setting 0111 0 0 0 0 0 0 0 0 0 1 0 0 10 110 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 --: don't care CXD3048R Command Preset Table ($4X to EX) cont. Register Data 5 Command DOUT subcode-Q setting 1001 DRAM I/F 1111 Compression setting EFM playability enhancement setting Sync expansion specification 0 0 0 0 0 0 0 0 0 0 0 0 Address Data 1 Data 2 Data 3 Data 4 D3 0000 0 D2 0 D1 0 D0 0 D3 D2 D1 D0 D3 D2 D1 D0 Data 6 Data 7 1110 0 0 0 0 0 0 0 0 0 0 0 0 A 1010 1010 0 0 0 0 0 1 0 0 1011 1 0 0 0 0 0 0 0 1 0 0 0 1100 1 0 0 0 0 0 0 1 - 40 - B C D Spindle servo setting Traverse monitor counter setting Spindle servo coefficient setting CLV CTRL 1011 1111 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1100 0 0 0 0 0 0 0 0 -- -- -- -- 1101 0 0 0 0 1 0 0 -- -- -- -- --: don't care CXD3048R CXD3048R (Coefficient ROM Preset Values Table (1)) ADDRESS K00 K01 K02 K03 K04 K05 K06 K07 K08 K09 K0A K0B K0C K0D K0E K0F K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K1A K1B K1C K1D K1E K1F K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K2A K2B K2C K2D K2E K2F DATA E0 81 23 7F 6A 10 14 30 7F 46 81 1C 7F 58 82 7F 4E 32 20 30 80 77 80 77 00 F1 7F 3B 81 44 7F 5E 82 44 18 30 7F 46 81 3A 7F 66 82 44 4E 1B 00 00 CONTENTS SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H FOCUS LOW BOOST FILTER A-L FOCUS LOW BOOST FILTER B-H FOCUS LOW BOOST FILTER B-L FOCUS PHASE COMPENSATE FILTER A FOCUS DEFECT HOLD GAIN FOCUS PHASE COMPENSATE FILTER B FOCUS OUTPUT GAIN ANTI SHOCK INPUT GAIN FOCUS AUTO GAIN HPTZC / Auto Gain HIGH PASS FILTER A HPTZC / Auto Gain HIGH PASS FILTER B ANTI SHOCK HIGH PASS FILTER A HPTZC / Auto Gain LOW PASS FILTER B Fix TRACKING INPUT GAIN TRACKING HIGH CUT FILTER A TRACKING HIGH CUT FILTER B TRACKING LOW BOOST FILTER A-H TRACKING LOW BOOST FILTER A-L TRACKING LOW BOOST FILTER B-H TRACKING LOW BOOST FILTER B-L TRACKING PHASE COMPENSATE FILTER A TRACKING PHASE COMPENSATE FILTER B TRACKING OUTPUT GAIN TRACKING AUTO GAIN FOCUS GAIN DOWN HIGH CUT FILTER A FOCUS GAIN DOWN HIGH CUT FILTER B FOCUS GAIN DOWN LOW BOOST FILTER A-H FOCUS GAIN DOWN LOW BOOST FILTER A-L FOCUS GAIN DOWN LOW BOOST FILTER B-H FOCUS GAIN DOWN LOW BOOST FILTER B-L FOCUS GAIN DOWN PHASE COMPENSATE FILTER A FOCUS GAIN DOWN DEFECT HOLD GAIN FOCUS GAIN DOWN PHASE COMPENSATE FILTER B FOCUS GAIN DOWN OUTPUT GAIN Not used Not used Fix indicates that normal preset values should be used. - 41 - CXD3048R - 42 - CXD3048R 1-4. Description of SENS Signals SENS output Microcomputer serial register ASEQ = 0 (latching not required) $0X $1X $2X $30 to $37 $38 $38 $39X $3A $3B to $3F $4X $5X $6X $A0 to $A8 $AA to $AF $BX $CX $EX $7X, 8X, 9X, DX, FX Z Z Z Z Z Z Z Z Z Z Z Z GFS COMP COUT OV64 Z ASEQ = 1 FZC AS TZC SSTP AGOK XAVEBSY See 5-18. Description of Commands and Data Sets "$39". FBIAS Count STOP SSTP XBUSY FOK 0 GFS COMP COUT OV64 0 Output data length -- -- -- -- -- -- 8 to 16 bits -- -- -- -- -- -- -- -- -- -- $38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases. - 43 - CXD3048R Description of SENS Signals SENS output Z XBUSY FOK GFS COMP The SENS pin is high impedance. Low while the auto sequencer is in operation, high when operation terminates. Outputs the same signal as the FOK pin. High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Counts the number of tracks set with Reg.B. High when Reg.B is latched, low when COUT is counted for the initial Reg.B number. Counts the number of tracks set with Reg.B. High when Reg.B is latched, toggles each time COUT is counted for the Reg.B number. While $44 and $45 are being executed, toggles with each COUT 8-count instead of the Reg.B number. Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter. COUT OV64 - 44 - CXD3048R 1-5. Description of Commands The meaning of the data for each address on the XLAT pin side is explained below. $4X commands Register name 4 Data 1 Command AS3 AS2 AS1 AS0 MT3 Data 2 MAX timer value MT2 MT1 MT0 LSSL Data 3 Timer range 0 0 0 Command Cancel Fine Search Focus-On 1 Track Jump 10 Track Jump 2N Track Jump M Track Move AS3 0 0 0 1 1 1 1 AS2 0 1 1 0 0 1 1 AS1 0 0 1 0 1 0 1 AS0 0 RXF 1 RXF RXF RXF RXF RXF = 0 Forward RXF = 1 Reverse * When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted. * When the Track jump commands ($44, $45 and $48 to $4D) are canceled, $25 is sent and the auto sequence is interrupted. MAX timer value MT3 23.2ms 1.49s MT2 11.6ms 0.74s MT1 5.8ms 0.37s MT0 2.9ms 0.18s LSSL 0 1 0 0 0 Timer range 0 0 0 0 0 0 * To disable the MAX timer, set the MAX timer value to "0". $5X commands Timer Blind (A, E), Overflow (C, G) Brake (B) TR3 0.18ms 0.36ms TR2 0.09ms 0.18ms TR1 0.045ms 0.09ms TR0 0.022ms 0.045ms - 45 - CXD3048R $6X commands Register name 6 Data 1 KICK (D) SD3 Timer When executing KICK (D) $44 or $45 When executing KICK (D) $4C or $4D Timer KICK (F) SD2 SD1 SD0 KF3 SD3 23.2ms 11.6ms KF3 0.72ms Data 2 KICK (F) KF2 KF1 SD2 11.6ms 5.8ms KF2 0.36ms KF0 SD1 5.8ms 2.9ms KF1 0.18ms SD0 2.9ms 1.45ms KF0 0.09ms $7X commands Auto sequence track jump count setting Command Auto sequence track jump count setting Data 1 D3 D2 D1 D0 D3 Data 2 D2 D1 29 D0 28 D3 27 Data 3 D2 26 D1 25 D0 24 D3 23 Data 4 D2 22 D1 21 D0 20 215 214 213 212 211 210 * This command is used to set N when a 2N-track jump is executed, to set M when an M-track move is executed and to set the jump count when fine search is executed for auto sequencer. * The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count depends on the mechanical limitations of the optical system. * When the track jump count is from 0 to 15, the COUT signal is counted for 2N-track jumps and M-track moves; when the count is 16 or over, the MIRR signal is counted. For fine search, the COUT signal is counted. - 46 - CXD3048R $8X commands Data 1 Command D3 D2 D1 D0 D3 Data 2 D2 D1 D0 CD- DOUT DOUT VCO VCO MODE WSEL ASHS SOCT0 SEL2 SEL1 specification ROM Mute Mute-F Command bit CDROM = 1 CDROM = 0 C2PO timing 1-3 1-3 Processing CDROM mode; average value interpolation and pre-value hold are not performed. Audio mode; average value interpolation and pre-value hold are performed. Command bit DOUT Mute = 1 DOUT Mute = 0 Processing When Digital Out is on ($B MD2 = 1), DOUT output is muted. When Digital Out is on, DOUT output is not muted. Command bit Processing DOUT Mute F = 1 When Digital Out is on ($B MD2 = 1), DA output is muted. DOUT Mute F = 0 DA output mute is not affected when Digital Out is either on or off. Other mute conditions 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MD2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 DOUT Mute DOUT Mute F DOUT output 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 - dB 0dB OFF DA output for 48-bit slot 0dB - dB 0dB - dB 0dB - dB See "Mute conditions" (1) to (5) under $AX commands for other mute conditions. When $A4 DTSL1 = 1, the Digital Out from the bass boost or shock-proof is selected. See the description of Digital Out. - 47 - CXD3048R Command bit WSEL = 1 WSEL = 0 Sync protection window width 26 channel clock 6 channel clock Application Anti-rolling is enhanced. Sync window protection is enhanced. In normal-speed playback, channel clock = 4.3218MHz. Command bit ASHS = 0 ASHS = 1 Function The command transfer rate from the auto sequencer to the DSSP block is set to normal speed. The command transfer rate from the auto sequencer to the DSSP block is set to half speed. See "4-8. CD-DSP Block Playback Speed" for settings. Command bit SOCT0 0 0 1 1 SOCT1 0 1 0 1 Processing Subcode-Q is output from the SQSO pin. The spindle speed measurement result is output from the SQSO pin. Input the readout clock to SQCK. (See Timing Chart 2-5.) Various signals are output from the SQSO pin. Input the readout clock to SQCK. (See Timing Chart 2-4.) The error rate is output from the SQSO pin. Input the readout clock to SQCK. (See Timing Chart 2-6.) $8X command TXOUT = 0 and $A8X command SDTO OUT = 0 must be set. Command Data 2 D3 D2 D1 D0 D3 KSL3 Data 3 D2 KSL2 D1 KSL1 D0 KSL0 MODE VCO VCO ASHS SOCT0 specification SEL2 SEL1 See above. Command bit VCOSEL2 = 0 VCOSEL2 = 1 Processing Multiplier PLL VCO2 is set to normal speed. Multiplier PLL VCO2 is set to approximately twice the normal speed. Command bit KSL3 0 0 1 1 KSL2 0 1 0 1 Processing Output of multiplier PLL VCO1 selected by VCO1 CS0 is 1/1 frequency-divided. Output of multiplier PLL VCO1 selected by VCO1 CS0 is 1/2 frequency-divided. Output of multiplier PLL VCO1 selected by VCO1 CS0 is 1/4 frequency-divided. Output of multiplier PLL VCO1 selected by VCO1 CS0 is 1/8 frequency-divided. - 48 - CXD3048R Command bit VCOSEL1 = 0 VCOSEL1 = 1 Processing Wide-band PLL VCO1 is set to normal speed. Wide-band PLL VCO1 is set to approximately twice the normal speed. Command bit KSL1 0 0 1 1 KSL0 0 1 0 1 Processing Output of wide-band PLL VCO2 is 1/1 frequency-divided. Output of wide-band PLL VCO2 is 1/2 frequency-divided. Output of wide-band PLL VCO2 is 1/4 frequency-divided. Output of wide-band PLL VCO2 is 1/8 frequency-divided. Block Diagram of VCO Internal Path VCO1SEL 1/1 No.1 VCO1 Selector Selector 1/2 To DSP interior 1/4 No.2 VCO1 VCO1CS0 1/8 KSL3, 2 VCO1 internal path VCO2SEL 1/1 Selector 1/2 VCO2 1/4 To DSP interior 1/8 KSL1, 0 VCO2 internal path - 49 - CXD3048R $8X commands cont. Command MODE specification Data 4 D3 0 D2 VCO1 CS0 D1 0 D0 0 D3 ERC4 Data 5 D2 D1 D0 D3 Data 6 D2 D1 D0 SCOR SCSY SOCT1 TXON TXOUT OUTL1 OUTL0 SEL See page 48. Command bit VCO1CS0 = 0 VCO1CS0 = 1 Selects the No. 1 VCO1. Selects the No. 2 VCO1. Processing The CXD3048R has two multiplier PLL VCO1s, and this command selects one of these VCO1s. The two VCOs are No. 2 and No. 1 in order of the maximum frequency. The block diagrams for VCO1 and VCO2 including VCOSEL1, VCOSEL2, KSL0 to KSL3 and VCO1CS0 shown on the previous page. Command bit ERC4 = 0 ERC4 = 1 Processing C2 error double correction is performed when DSPB = 1. C2 error quadruple correction is performed even when DSPB = 1. Command bit SCOR SEL = 0 SCOR SEL = 1 WDCK signal is output. Processing GRSCOR (protected SCOR) is output. Used when outputting GRSCOR from the WDCK pin. Command bit SCSY = 0 SCSY = 1 No processing. GRSCOR (protected SCOR) synchronization is applied again. Processing Used to resynchronize GRSCOR. The rising edge signal of this command bit is used internally, so when resynchronizing GRSCOR, first return the setting to "0" and then set to "1". GRSCOR is the crystal accuracy SCOR signal obtained by removing the motor wow component. This signal is synchronized with PCMDATA. The resynchronization conditions are when GTOP = high. Command bit TXON = 0 TXON = 1 Processing When CD TEXT data is not demodulated, set TXON to "0". When CD TEXT data is demodulated, set TXON to "1". See "4-16. CD TEXT Data Demodulation". - 50 - CXD3048R Command bit TXOUT = 0 TXOUT = 1 Processing Various signals except for CD TEXT are output from the SQSO pin. CD TEXT data is output from the SQSO pin. See "4-16. CD TEXT Data Demodulation". Command bit OUTL1 = 0 OUTL1 = 1 WDCK and XPCK are output. WDCK and XPCK outputs are set low. Processing Command bit OUTL0 = 0 OUTL0 = 1 PCMD, BCK and LRCK are output. Processing PCMD, BCK and LRCK outputs are set low. Command MODE specification Data 7 D3 0 D2 0 D1 OUTL2 D0 0 Command bit OUTL2 = 0 OUTL2 = 1 WFCK is output. WFCK is set low. Processing The $A7X command XOE OUT must be set to "0". - 51 - CXD3048R $9X commands Command Function specification Data 1 D3 1 D2 D1 D0 1 D3 BiliGL MAIN Data 2 D2 BiliGL SUB D1 FLFC D0 0 DSPB ASEQ ON-OFF ON-OFF Command bit DSPB = 0 DSPB = 1 Processing Normal-speed playback, C2 error quadruple correction. Double-speed playback, C2 error double correction. (quadruple correction when ERC4 = 1) Normally FLFC = 0. In CAV-W mode, set FLFC to "1" independently of the playback speed. Command bit BiliGL SUB = 0 BiliGL SUB = 1 BiliGL MAIN = 0 STEREO SUB BiliGL MAIN = 1 MAIN Mute Definition of bilingual capable MAIN, SUB and STEREO The left channel input is output to the left and right channels for MAIN. The right channel input is output to the left and right channels for SUB. The left and right channel inputs are output to the left and right channels, respectively, for STEREO. Data 3 Command Function specification D3 0 D2 0 D1 0 D0 0 D3 1 Data 4 D2 0 D1 0 D0 1 D3 0 Data 5 D2 0 D1 0 D0 0 Data 6 D3 0 D2 0 D1 0 D0 0 D3 DIV4 Data 7 D2 0 D1 0 D0 0 This switches the digital PLL master clock. Either the conventional mode or the 2/3 mode (2/3 of the conventional clock) can be selected. Command bit DIV4 = 0 DIV4 = 1 Digital PLL master clock; 2/3 mode. Processing Digital PLL master clock; conventional mode. (preset) Note) Do not set DIV4 to "1" when DSPB = 0. - 52 - CXD3048R $AX commands Command Audio CTRL Data 1 D3 0 D2 0 D1 Mute D0 ATT D3 PCT1 Data 2 D2 PCT2 D1 0 D0 SOC2 Command bit Mute = 0 Mute = 1 Meaning Mute off if other mute conditions are not set. Mute on. Peak register reset. Command bit ATT = 0 ATT = 1 Meaning Attenuation off. -12dB Mute conditions (1) When register A mute = 1. (2) When register 8 DOUT Mute F = 1 and Digital Out is on ($B command MD2 = 1). (3) When GFS stays low for over 35ms (during normal-speed). (4) When register 9 BiliGL MAIN = Sub = 1. (5) When register A PCT1 = 1 and PCT2 = 0. (1) to (3) perform zero-cross muting with a 1ms time limit. Command bit PCT1 0 0 1 1 PCT2 0 1 0 1 Meaning Normal mode Level meter mode Peak meter mode Normal mode PCM Gain x 0dB x 0dB Mute x 0dB ECC error correction ability C1: double; C2: quadruple C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double Description of level meter mode (see Timing Chart 1-4.) * When the LSI is set to this mode, it performs digital level meter functions. * When the 96-bit clock is input to SQCK, 96 bits of data are output to SQSO. The initial 80 bits are subcode-Q data (see "[2] Subcode Interface"). The last 16 bits are LSB first, which are 15-bit PCM data (absolute values) and an L/R flag. The final bit (L/R flag) is high when the 15-bit PCM data is from the left channel and low when the data is from the right channel. * The PCM data is reset and the L/R flag is inverted after one readout. Then the measurement for the maximum value continues until the next readout. - 53 - CXD3048R Description of peak meter mode (see Timing Chart 1-5.) * When the LSI is set to this mode, the maximum PCM data value is detected regardless of if it comes from the left or right channel. The 96-bit clock must be input to SQCK to read out this data. * When the 96-bit clock is input, 96 bits of data are output to SQSO and the value is set in the LSI internal register again. In other words, the PCM maximum value register is not reset by the readout. * To reset the PCM maximum value register to "0", set PCT1 = PCT2 = 0 or set the $AX command Mute. * The subcode-Q absolute time is automatically controlled in this mode. In other words, after the maximum value is generated, the absolute time for CRC to become OK is retained in the memory. Normal operation is conducted for the relative time. * The final bit (L/R flag) of the 96-bit data is normally "0". * The pre-value hold and average value interpolation data are fixed to level (- ) for this mode. Command bit SOC2 = 0 SOC2 = 1 Processing The SENS signal is output from the SENS pin as usual. The SQSO pin signal is output from the SENS pin. SENS output switching * This command is used to output the SQSO pin signal from the SENS pin. When SOC2 = 0, SENS output is performed as usual. When SOC2 = 1, the SQSO pin signal is output from the SENS pin. At this time, the readout clock is input to the SCLK pin. Note) Perform the SOC2 switching when SQCK = SCLK = high. Command Audio CTRL Data 3 D3 0 D2 0 D1 0 D0 0 D3 0 Data 4 D2 1 D1 0 D0 0 D3 0 Data 5 D2 0 D1 0 D0 0 D3 0 Data 6 D2 0 D1 0 D0 0 - 54 - CXD3048R $A4 commands (preset: $A4C800) Command A4 (Signal select) Data 1 D3 0 D2 1 D1 0 D0 0 D3 Data 2 D2 D1 0 D0 0 D3 Data 3 D2 D1 D0 D3 0 Data 4 D2 D1 D0 RSL1 RSL0 DTSL DTSL MCSL MCSL 1 0 1 0 Data 6 SDSL SDSL SDSL 2 1 0 Data 7 Data 5 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 EN CKOUT CKOUT SLD max max max max max max max max XSOE SL2 SL1 BBIN C2PO7 C2PO6 C2PO5 C2PO4 C2PO3 C2PO2 C2PO1 C2PO0 RSL1, RSL0: These bits set the external buffer RAM. RSL1 0 1 1 RSL0 0 0 1 Processing The external buffer RAM is set to 4M bits. No selected. The external buffer RAM is set to 16M bits. : preset DTSL1, DTSL0: See the second half of the description of $A4 commands. MCSL1: This bit sets the DAC block master clock. When "0", the DAC block master clock is set to 16.9344MHz (384fs). (default) When "1", the DAC block master clock is set to 33.8688MHz (768fs). MCSL0: This bit sets the shock-proof memory controller block master clock. When "0", the shock-proof memory controller block master clock is set to 16.9344MHz (384fs). (default) When "1", the shock-proof memory controller block master clock is set to 33.8688MHz (768fs). ENXSOE: This bit switches the command input method. When "0", the command transfer clock and the SENS serial data readout clock are input from the respective pins. (default) When "1", the command transfer clock and the SENS serial data readout clock are input from the CLOK pin. The clock input is switched with the XSOE pin. At this time, connect the SCLK pin to high. ENXSOE 0 0 1 1 XSOE pin L H L H CLOK pin Command transfer clock input Command transfer clock input SENS serial data readout clock input Command transfer clock input SCLK pin SENS serial data readout clock input SENS serial data readout clock input Connect to high. Connect to high. In addition, when ENXSOE is set to "1" and the SQSO pin signal output is read from the SENS pin, the command input method is as follows. At this time, connect the SCLK and SQCK pins to high. See the command descriptions for $A command SOC2 and $8 commands TXOUT, SOCT0 and SOCT1. - 55 - CXD3048R $A8 $8 $8 $8 ENXS XSOE $A SDTO TX SOC SOC OE pin SOC2 OUT OUT T0 T1 1 1 1 1 1 1 1 1 H L L L L L L L 0 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 1 CLOK pin Command transfer clock input SENS serial data readout clock input Subcode-Q readout clock input SENS pin High or low output SENS output1 Subcode-Q output Readout clock input of Spindle speed measurement the spindle speed result output2 measurement result Various signal readout Various signal output3 clock input Error rate readout clock input CD TEXT data readout clock input Error rate output4 CD TEXT data output Readout clock input of Shock-proof memory controller shock-proof memory serial data output controller serial data : don't care 1 See "1-4. Description of SENS Signals" for the SENS output. 2 See Timing Chart 2-5 for the spindle speed measurement result. 3 The output signals are PER7 to PER0, FOK, GFS, LOCK, EMPH, ALOCK and VF9 to VF0. For details, see Timing Chart 2-4. 4 For the error rate timing, see Timing Chart 2-6. CKOUTSL2, CKOUTSL1: These bits select the clock output from the R4M pin. When the crystal is 16.9344MHz and XTSL = high, the output frequency is halved. CKOUTSL2 CKOUTSL1 0 0 1 1 0 1 0 1 4.2336MHz output 8.4672MHz (R8M) output 4.2336MHz (C4M) output Changes in CAV-W mode and variable pitch mode. : preset DTSL1, DTSL0: These bits select the data output from the DOUT pin. In external mode, the data input through the LRCKI, BCKI and PCMDI pins is used. DOUT output in the following tables is valid when $34A commands DOUT EN1 and DOUT EN2 are both 1. In this case, see "$34A commands". When $34A commands DOUT EN1 and DOUT EN2 are both 0, see "4-5-2. Digital Out from DA Interface Input". At this time, the data from the CD DSP is output from the DOUT pin with a subcode is added. - 56 - Processing CXD3048R SDSL2, SDSL1: These bits select the data input to the DAC block and the data output from the PCMD pin. SLDBBIN: This bit selects the data input to the DAC block and the data output from the PCMD and DOUT pins. max C2PO7 to max C2PO0: These bits set the C2PO conditions. max C2PO7 to max C2PO0 00000000 to 11111111 Ptocessing The C2PO upper limit value reflected to mon C2PO and added to the write prohibited condition. When SLDBBIN = 0, the internally connected data is selected. (default) DTSL1 DTSL0 SDSL2 SDSL1 SDSL0 Input to DAC block 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DSP mode DOUT output DSP & DAC mode PCMD output DSP mode DSP & DAC mode Shock-proof memory controller mode Shock-proof memory controller & DAC mode DSP mode DSP & DAC mode Shock-proof memory controller mode Shock-proof memory controller & DAC mode DSP mode DSP mode DSP mode Shock-proof memory controller mode DSP mode Shock-proof memory controller mode : preset 1: The relationship between LRCK, BCK and PCMD changes according to the setting value. When SDSL0 = 0, the LRCK, BCK and PCMD phase difference is constant but the LRCK frequency changes when SDSL0 is switched. When SDSL0 = 1, the LRCK frequency is constant but the phase difference between LRCK, BCK and PCMD changes before and after SDSL1 is switched. When not switching the output data selection, set SDSL1 and SDSL0 to the same value. - 57 - External mode DSP & DAC mode Shock-proof memory controller mode Shock-proof memory controller & DAC mode DSP mode DSP & DAC mode Shock-proof memory controller mode Shock-proof memory controller & DAC mode Shock-proof Shock-proof memory controller memory controller mode & DAC mode DSP mode DSP mode Shock-proof Shock-proof memory controller memory controller mode mode CXD3048R When SLDBBIN = 1, the data input from the LRCKI, BCKI and PCMDI pins is selected. DTSL1 DTSL0 SDSL2 SDSL1 SDSL0 Input to DAC block 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 External mode External mode DSP mode Shock-proof memory controller mode External & DAC mode DOUT output PCMD output DSP mode External & DAC mode Shock-proof memory controller mode External & DAC mode DSP mode External & DAC mode Shock-proof memory controller mode External & DAC mode DSP mode External & DAC mode DSP mode Shock-proof memory controller mode External & DAC mode DSP mode External & DAC mode Shock-proof memory controller mode External & DAC mode 1: The relationship between LRCK, BCK and PCMD changes according to the setting value. When SDSL0 = 0, the LRCK, BCK and PCMD phase difference is constant but the LRCK frequency changes when SDSL0 is switched. When SDSL0 = 1, the LRCK frequency is constant but the phase difference between LRCK, BCK and PCMD changes before and after SDSL1 is switched. When not switching the output data selection, set SDSL1 and SDSL0 to the same value. - 58 - CXD3048R $A5 commands (when Data 2 D3 = 0, D2 = 0) (preset: $A504000) Command A5 (Bass boost) Data 1 D3 0 D2 1 D1 0 D0 1 D3 0 Data 2 D2 0 D1 1 D0 D3 Data 3 D2 D1 D0 D3 Data 4 D2 D1 D0 ZMUT SMUT AD10 AD9 AD8 AD7 AD6 AD5 AD4 A Data 5 D3 D2 D1 D0 D3 Data 6 D2 0 D1 0 D0 0 AD3 AD2 AD1 AD0 setup ZMUTA: SMUT: AD10 to AD0: This bit sets the zero detection analog mute on/off. When "0", zero detection analog mute is on. (default) When "1", zero detection analog mute is off. When zero data is detected for both the left and right channels, the LPF block output is set to center output. This bit sets the soft mute on/off. When "0", soft mute is off. (default) When "1", soft mute is on. These bits set the attenuation data. The attenuation data consists of 11 bits, and is set as follows. Attenuation data 7FF (h) 7FE (h) : 402 (h) 401 (h) 400 (h) 3FF (h) 3FE (h) : 001 (h) 000 (h) : preset The audio output from 001 (h) to 7FF (h) is obtained using the following equation: Audio data output = 20 log Attenuation data 1024 [dB] Audio output +6.02dB +6.016dB : +0.017dB +0.0085dB 0dB -0.0085dB -0.017dB : -60.206dB - setup: This bit can shorten the rise time of the VREFL and VREFR pins. When "0", the rise time is not shortened. (default) (Recommendation setting when the external capacitance is 1F or less.) When "1", the rise time is shortened. (Recommendation setting when the external capacitance exceeds 1F.) Return setup to 0 after the VREFL and VREFR pins rise. (setup = 0 for normal use) - 59 - CXD3048R $A5 commands (when Data 2 D3 = 0, D2 = 1) (preset: $A540A4) Command A5 (Bass boost) Data 1 D3 0 D2 1 D1 0 D0 1 D3 0 Data 2 D2 1 D1 D0 D3 Data 3 D2 D1 D0 D3 1 Data 4 D2 D1 D0 PWDN ZDPL WOC DAC HiCut BST EMPH FILTER CL PDM OBIT OBIT SEL 1 0 Data 5 D3 0 PWDN: D2 1 D1 0 D0 0 ZDPL: WOC: DAC EMPH: HiCutFILTER: BSTCL: PDMSEL: This bit sets the DAC block operation mode. When "0", the DAC block clock is stopped. This makes it possible to reduce power consumption. (default) The zero detection flag for the headphone volume circuit side is output from the LRMU pin. When "1", the DAC block operates normally. This bit sets the zero detection flag polarity. When "0", the LRMU pin is set low during mute. (default) When "1", the LRMU pin is set high during mute. When WOC = 1, the DAC sync window opens. This is used to synchronize the DAC. This bit sets the digital de-emphasis on/off. When "0", digital de-emphasis is off. (default) When "1", digital de-emphasis is on. This bit sets the high-cut filter on/off. When "0", the high-cut filter is off. (default) When "1", the high-cut filter is on. This bit sets the bass boost level clear on/off. 1: On; the set bass boost level is cleared to 0dB. 0: Off; normal operation (default) This bit switches the PDM signal output from the DAC block. When "0", connect the external resistors and capacitors to the VREFL and VREFR pins. (default) When "1", connect the external capacitors to the VREFL and VREFR pins. 100 Analog out 2200pF 22k VREFL (R) 22k 1F VREFL (R) 1F AOUT1 (2) 2200pF Analog out 100 AOUT1 (2) LPF external circuit example (PDMSEL = 0) OBIT1, OBIT0: LPF external circuit example (PDMSEL = 1) These bits set the word length of the serial data output from the PCMD pin. The serial data word length can be selected only when the data output from the PCMD pin is set to DAC output. OBIT1 0 0 1 OBIT0 0 1 0 Serial data word length 20 bits 18 bits 16 bits - 60 - : preset CXD3048R $A5 commands (when Data 2 D3 = 1, D2 = 0) (preset: $A58000) Command A5 (Bass boost) Data 1 D3 0 D2 1 D1 0 D0 1 D3 1 Data 2 D2 0 D1 D0 D3 Data 3 D2 D1 D0 D3 Data 4 D2 D1 D0 BBON BBON HBON HBON BBSL BBSL HBSL HBSL BBST BBST 1 0 Vdwn1 Vdwn0 1 0 1 0 1 0 Data 5 D3 D2 D1 D0 BBST BBST BBST BBST Vup1 Vup0 Uth Lth BBON1, BBON0: These bits set the bass boost on/off and the turnover frequency. BBON1 0 0 1 1 BBON0 0 1 0 1 Bass boost is off. Bass boost is on and the turnover frequency is set to 125Hz. Bass boost is on and the turnover frequency is set to 160Hz. Bass boost is on and the turnover frequency is set to 200Hz. : preset HBON1, HBON0: These bits set the high boost on/off and the turnover frequency. HBON1 0 1 1 HBON0 0 0 1 High boost is off. High boost is on and the turnover frequency is set to 5kHz. High boost is on and the turnover frequency is set to 7kHz. : preset BBSL1, BBSL0: These bits set the boost level for bass boost. BBSL1 0 0 1 1 BBSL0 0 1 0 1 Processing The boost level for bass boost is set to 10dB. The boost level for bass boost is set to 14dB. The boost level for bass boost is set to 18dB. The boost level for bass boost is set to 22dB. : preset HBSL1, HBSL0: These bits set the boost level for high boost. HBSL1 0 0 1 1 HBSL0 0 1 0 1 Processing The boost level for high boost is set to 4dB. The boost level for high boost is set to 6dB. The boost level for high boost is set to 8dB. The boost level for high boost is set to 10dB. : preset - 61 - Processing Processing CXD3048R BBST Vdwn1, BBST Vdwn0: These bits set the boost attack time (Vol Down) for bass and high boost. BBST Vdwn1 BBST Vdwn0 0 0 1 0 1 1 Processing The boost attack time for bass and high boost is set to standard. The boost attack time for bass and high boost is set to fast. The boost attack time for bass and high boost is set to slow. : preset BBST Vup1, BBST Vup0: These bits set the boost release time (Vol Up) for bass and high boost. BBST Vup1 BBST Vup0 0 0 1 0 1 1 Processing The boost release time for bass and high boost is set to standard. The boost release time for bass and high boost is set to fast. The boost release time for bass and high boost is set to slow. : preset This bit sets the bass and high boost Uth. When "0", Uth is set to -1.9dB. (default) When "1", Uth is set to -0.9dB. BBST Lth: This bit sets the bass and high boost Lth. When "0", Lth is set to -12dB. (default) When "1", Lth is set to -4.4dB. When the volume rises above Uth, the boost level is reduced. The speed at which the boost level is reduced is the attack time. When the volume falls below Lth, the boost level is increased up to the setting value. The speed at which the boost level is increased is the release time. $A5 commands (when Data 2 D3 = 1, D2 = 1) (preset: $A5C000) Command A5 (Bass boost) Data 1 D3 0 D2 1 D1 0 D0 1 D3 1 Data 2 D2 1 D1 COMP ON D0 0 D3 0 Data 3 D2 0 D1 0 D0 0 D3 0 Data 4 D2 0 D1 1 D0 0 BBST Uth: Data 5 D3 0 D2 0 D1 0 D0 PDM INV COMP ON: PDM INV: This bit sets the compressor on/off. When "0", the compressor is off. (default) When "1", the compressor is on. This bit sets the DAC block PDM signal polarity. When "0", the polarity is set to non-inverted. (default) When "1", the polarity is set to inverted. - 62 - CXD3048R $A6 commands (when Data 2 D3 = 0, D2 = 0) (preset: $A604000) Data 1 Command A6 (Headphone) D3 0 D2 1 D1 1 D0 0 D3 0 Data 2 D2 0 D1 1 D0 0 D3 Data 3 D2 D1 D0 D3 Data 4 D2 D1 D0 SMUT AD10 AD9 AD8 AD7 AD6 AD5 AD4 Data 5 D3 D2 D1 D0 AD3 AD2 AD1 AD0 SMUT: AD10 to AD0: This bit sets the soft mute on/off. When "0", soft mute is off. (default) When "1", soft mute is on. These bits set the attenuation data. The attenuation data consists of 11 bits, and is set as follows. Attenuation data 7FF (h) 7FE (h) : 402 (h) 401 (h) 400 (h) 3FF (h) 3FE (h) : 001 (h) 000 (h) : preset The audio output from 001 (h) to 7FF (h) is obtained using the following equation: Audio data output = 20 log Attenuation data 1024 [dB] Audio output +6.02dB +6.016dB : +0.017dB +0.0085dB 0dB -0.0085dB -0.017dB : -60.206dB - - 63 - CXD3048R $A6 commands (when Data 2 D3 = 0, D2 = 1) (preset: $A640A4) Command A6 (Headphone) Data 1 D3 0 D2 1 D1 1 D0 0 D3 0 Data 2 D2 1 D1 D0 D3 Data 3 D2 D1 D0 D3 1 Data 4 D2 PDM SEL D1 0 D0 0 PWDN ZDPL WOC DAC HiCut BST EMPH FILTER CL Data 5 D3 0 PWDN: D2 1 D1 0 D0 0 ZDPL: WOC: DAC EMPH: HiCutFILTER: BSTCL: PDMSEL This bit sets the headphone block operation mode. When "0", the headphone block clock is stopped. This makes it possible to reduce power consumption. (default) When "1", the headphone block operates normally. This bit sets the zero detection flag polarity. The zero detection flag for the headphone volume circuit is output from the LRMU pin when $A6 PWDN = 0. When "0", the LRMU pin is set low during mute. (default) When "1", the LRMU pin is set high during mute. When WOC = 1, the headphone sync window opens. This is used to synchronize the DAC. This bit sets the digital de-emphasis on/off. When "0", digital de-emphasis is off. (default) When "1", digital de-emphasis is on. This bit sets the high-cut filter on/off. When "0", the high-cut filter is off. (default) When "1", the high-cut filter is on. This bit sets the bass boost level clear on/off. 1: On; the set bass boost level is cleared to 0dB. 0: Off; normal operation (default) This bit switches the PDM signal output from the headphone block. 1 output PDMSEL = 0 PDMSEL = 1 0 output 1 output 0 output Left channel side waveform (Right channel side waveform is inverted.) - 64 - CXD3048R $A6 commands (when Data 2 D3 = 1, D2 = 0) (preset: $A68000) Command A6 (Headphone) Data 1 D3 0 D2 1 D1 1 D0 0 D3 1 Data 2 D2 0 D1 D0 D3 Data 3 D2 D1 D0 D3 Data 4 D2 D1 D0 BBON BBON HBON HBON BBSL BBSL HBSL HBSL BBST BBST 1 0 Vdwn1 Vdwn0 1 0 1 0 1 0 Data 5 D3 D2 D1 D0 BBST BBST BBST BBST Vup1 Vup0 Uth Lth BBON1, BBON0: These bits set the bass boost on/off and the turnover frequency. BBON1 0 0 1 1 BBON0 0 1 0 1 Bass boost is off. Bass boost is on and the turnover frequency is set to 125Hz. Bass boost is on and the turnover frequency is set to 160Hz. Bass boost is on and the turnover frequency is set to 200Hz. : preset HBON1, HBON0: These bits set the high boost on/off and the turnover frequency. HBON1 0 1 1 HBON0 0 0 1 High boost is off. High boost is on and the turnover frequency is set to 5kHz. High boost is on and the turnover frequency is set to 7kHz. : preset BBSL1, BBSL0: These bits set the boost level for bass boost. BBSL1 0 0 1 1 BBSL0 0 1 0 1 Processing The boost level for bass boost is set to 10dB. The boost level for bass boost is set to 14dB. The boost level for bass boost is set to 18dB. The boost level for bass boost is set to 22dB. : preset HBSL1, HBSL0: These bits set the boost level for high boost. HBSL1 0 0 1 1 HBSL0 0 1 0 1 Processing The boost level for high boost is set to 4dB. The boost level for high boost is set to 6dB. The boost level for high boost is set to 8dB. The boost level for high boost is set to 10dB. : preset - 65 - Processing Processing CXD3048R BBST Vdwn1, BBST Vdwn0: These bits set the boost attack time (Vol Down) for bass and high boost. BBST Vdwn1 BBST Vdwn0 0 0 1 0 1 1 Processing The boost attack time for bass and high boost is set to standard. The boost attack time for bass and high boost is set to fast. The boost attack time for bass and high boost is set to slow. : preset BBST Vup1, BBST Vup0: These bits set the boost release time (Vol Up) for bass and high boost. BBST Vup1 BBST Vup0 0 0 1 0 1 1 Processing The boost release time for bass and high boost is set to standard. The boost release time for bass and high boost is set to fast. The boost release time for bass and high boost is set to slow. : preset BBST Uth: This bit sets the bass and high boost Uth. When "0", Uth is set to -1.9dB. (default) When "1", Uth is set to -0.9dB. BBST Lth: This bit sets the bass and high boost Lth. When "0", Lth is set to -12dB. (default) When "1", Lth is set to -4.4dB. When the volume rises above Uth, the boost level is reduced. The speed at which the boost level is reduced is the attack time. When the volume falls below Lth, the boost level is increased up to the setting value. The speed at which the boost level is increased is the release time. $A6 commands (when Data 2 D3 = 1, D2 = 1) (preset: $A6C000) Command A6 (Headphone) Data 1 D3 0 D2 1 D1 1 D0 0 D3 1 Data 2 D2 1 D1 COMP ON D0 0 D3 0 Data 3 D2 0 D1 0 D0 0 D3 0 Data 4 D2 0 D1 1 D0 0 Data 5 D3 0 COMP ON: This bit sets the compressor on/off. When "0", the compressor is off. (default) When "1", the compressor is on. This bit sets the headphone block PDM signal polarity. When "0", the polarity is set to non-inverted. (default) When "1", the polarity is set to inverted. - 66 - D2 0 D1 0 D0 PDM INV PDM INV: CXD3048R $A7 commands (preset: $A7200000) Command A7 (Shock-proof memory setting) Data 1 D3 0 D2 1 D1 1 D0 1 D3 Data 2 D2 D1 D0 D3 Data 3 D2 D1 D0 D3 Data 4 D2 D1 D0 SL SL GTOP NOLIM SPSL READ REF REF XOE MSL2 MSL1 MSL0 XQOK XWRE CHECK WDCK COM 2 SEL ON OUT Data 5 D3 D2 D1 0 D0 D3 Data 6 D2 D1 D0 D3 Data 7 D2 D1 D0 ADDRST ADR SEL MO SL XQOK: STA XWI XWI SPSL WQR A11 READ READ MON S1 SEL SEL H2 H1 COM MON SEL S2 This bit sets the XQOK control mode. When "0", XQOK should be controlled for the period from when SCOR goes high until GRSCOR goes high. (default) When "1", XQOK should be controlled for the period while GRSCOR is high. SL XWRE: This bit sets the XWRE control mode. When "0", XWRE should be controlled for the period from when SCOR goes high until GRSCOR goes high. (default) When "1", XWRE should be controlled for the period while GRSCOR is high. GTOP CHECK: This bit controls GRSCOR generation when GTOP is high. When "0", the GRSCOR generation circuit is not resynchronized even when GTOP is high. When "1", the GRSCOR generation circuit is resynchronized when GTOP goes high. (default) NOLIM WDCK: Always set to "1". SPSL COM: This bit sets whether to control XQOK, XWRE and XRDE with pins or serial data. When "0", XQOK, XWRE and XRDE should be controlled with pins. (default) When "1", XQOK, XWRE and XRDE should be controlled with serial data ($A8). Note) The Data 3 D3 and Data 6 D1 bits should be switched somultaneously. READ2, READS2, READS1: This bit sets the audio data readout speed from the shock-proof memory controller block. READ2 READS2 READS1 0 0 0 0 1 0 0 1 1 0 1 0 1 Readout speed setting 1x speed readout 0.5x speed readout 0.25x speed readout -- 2x speed readout : preset The shock-proof memory controller interior should be resynchronized after the readout speed is switched. Execute the $AAX ADPWO command for resynchronization. - 67 - CXD3048R REF SEL: This bit sets the DRAM refresh rate. (Use this bit in conjunction with the $AC command REFSEL2.) REFSEL2 REFSEL 0 0 1 1 0 1 0 1 Reflesh rate 11.51ms/2048 times 5.81ms/2048 times 46.44ms/2048 times 23.22ms/2048 times : preset This bit sets the DRAM refresh function on/off. When "0", the refresh function is off. (default) When "1", the refresh function is on. XOE OUT: This bit switches the WFCK pin output mode. When "0", WFCK is output from the WFCK pin. (default) When "1", XOE is output from the WFCK pin. MSL2 to MSL0: These bits set the DRAM area that can be accessed from the microcomputer. MSL2 0 0 0 0 1 1 1 1 MSL1 0 0 1 1 0 0 1 1 MSL0 0 1 0 1 0 1 0 1 DRAM area that can be accessed from the microcomputer The entire DRAM area can be used as audio data. 32K bits 64K bits 128K bits 256K bits 512K bits 1M bits 2M bits : preset ADDRST SEL: This bit selects the address reset mode. When "0", the conventional address reset is used. (default) When "1", the address is reset by the ADDRST command. This bit selects the remaining valid addresses. When "0", the conventional remaining valid addresses are displayed. (default) When "1", the remaining addresses from 0000000 to 1111111 are displayed. The XWIH condition addition is selected. When "0", the condition is added. (default) When "1", the write speed condition is added to the write prohibited condition. The XWIH condition addition is selected. When "0", the condition is not added. (default) When "1", the condition of failure access to DRAM is added to the write prohibited condition. This bit selects the XWRE, XQOK and XRDE outputs. When "0", XWRE, XQOK and XRDE output is prohibited. (default) When "1", XWRE, XQOK and XRDE output is allowed. - 68 - REF ON: ADRMO: XWIH2: XWIH1: WQR MON: CXD3048R A11 SEL: STA SEL: This bit selects the A11 pin function. When "0", the A11 pin is used as the A11 pin. (default) When "1", the A11 pin is used as a low-active write prohibit factor. This bit selects the shock-proof memory controller status output. When "1", the conventional ESP status is output. (See 4-13-3.) When "0", the new shock-proof memory controller status is output. (default) The status readout when STA SEL = 0 is as follows. Signal D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 XFUL ROF SPOVER NOWR -- XWPHD QRCVD XEMP monC2PO GTOP -- AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 -- -- monADPCM 0: Write prohibited 1: Address updated 0: No valid data 1: C2PO of the setting value or higher present 1: GTOP present in the preceding GRSCOR Don't care. Address monitor Address monitor Address monitor Address monitor Address monitor Address monitor Address monitor Address monitor Address monitor Don't care. Don't care. 1: ADPCM compression error 0: No write area 1: The DSP SRAM has overflowed. 1: The speed limit is exceeded for more than the set number during one GRSCOR. 1: Access is failed in the shock-proof memory controller. Don't care. Description monGRSCOR 1: GRSCOR present MONSEL: This bit selects the COUT, XUGF, MIRR and XPCK pin functions. When "0", these pins output the signals corresponding to the SRO1, MTSL1 and MTSL0 commands. (See the table on page 8.) When "1", these pins output SCOR, QRCVD and GTOP, respectively. - 69 - CXD3048R $A8 commands (preset: $A8F8) Command A8 (Shock-proof memory control) Data 1 D3 1 D2 0 D1 0 D0 0 D3 Data 2 D2 D1 D0 D3 Data 3 D2 D1 0 D0 SDTO OUT XQOK XWRE XRDE XSOEO XSOEO ADDR ST 2 XQOK, XWRE, XRDE: When $A7 command SPSL COM = 1, XQOK, XWRE and XRDE are controlled with serial data. (default: 1) XSOEO: This bit controls the serial data from the shock-proof block. Shock-proof block data is loaded to the serial readout register by detecting the falling edge of XSOEO. XSOEO2: This bit is used when the microcomputer reads data from the DRAM. (default: 1) The shock-proof memory controller block loads the data from the DRAM to the serial readout register by detecting the fall of XSOEO2. ADDRST: This command is valid when $A7 command ADDRST SEL = 1. When "0", no operations are performed. (default) When "1", the VWA, WA and RA are all reset. SDTO OUT: This bit is used to output serial data from the shock-proof block to the SQSO pin. When "0", various signals are output from the SQSO pin. For details on these signals, see $8X commands SOCT1, SOCT0 and TXOUT. (default) When "1", the shock-proof block serial data is output from the SQSO pin. - 70 - CXD3048R $A9 commands (preset: $A90000) Command A9 (DOUT subcode-Q setting) Data 1 D3 1 D2 0 D1 0 D0 1 D3 Data 2 D2 D1 D0 D3 0 Data 3 D2 0 D1 0 D0 0 D3 Data 4 D2 D1 D0 SubQ SubQ SubQ SubQ A3 A2 A1 A0 Data 5 D3 D2 D1 D0 SubQ SubQ SubQ SubQ D7 D6 D5 D4 Data 7 Data 6 D3 D2 D1 D0 D3 D2 D1 D0 SubQ SubQ SubQ SubQ D3 D2 D1 D0 SubQA3 to SubQA0, SubQD7 to SubQD0: These bits set the Ubit inside the DOUT generation circuit in the DAC block. Note that these bits have no effect on the DOUT generation circuit in the CD DSP block. SubQA3 SubQA2 SubQA1 SubAD0 SubQD7 SubQD6 SubQD5 SubQD4 SubQD3 SubQD2 SubQD1 SubQD0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Q1 Q9 Q17 Q25 Q33 Q41 Q49 Q57 Q65 Q73 DON Q2 Q10 Q18 Q26 Q34 Q42 Q50 Q58 Q66 Q74 Q3 Q11 Q19 Q27 Q35 Q43 Q51 Q59 Q67 Q75 Q4 Q12 Q20 Q28 Q36 Q44 Q52 Q60 Q68 Q76 Q5 Q13 Q21 Q29 Q37 Q45 Q53 Q61 Q69 Q77 Q6 Q14 Q22 Q30 Q38 Q46 Q54 Q62 Q70 Q78 0 Q7 Q15 Q23 Q31 Q39 Q47 Q55 Q63 Q71 Q79 0 Q8 Q16 Q24 Q32 Q40 Q48 Q56 Q64 Q72 Q80 0 Setting contents Control, address Movement number INDEX number Elapsed time within a movement (minutes) Elapsed time within a movement (seconds) Elapsed time within a movement (frames) (Set to "0".) Absolute time (minutes) Absolute time (seconds) Absolute time (frames) (Control command) DCL DUP1 DUP0 DLD DON: This bit sets the Ubit output on/off inside the DOUT generation circuit in the DAC block. When "0", Ubit is not output. (default) When "1", Ubit is output. DCL: This bit clears the elapsed time within a movement to "0". The elapsed time is cleared to "0" at the falling edge of DCL (DCL = 1 0). (default: DCL = 1) DUP1: This bit sets the absolute time counter operate/stop. When "0", the absolute time counter is stopped. (default) When "1", the absolute time counter operates. DUP0: This bit sets the elapsed time within a movement counter operate/stop. When "0", the elapsed time within a movement counter is stopped. (default) When "1", the elapsed time within a movement counter operates. DLD: This bit is used when setting the INDEX number, elapsed time within a movement, and absolute time. When "0", the settings cannot be changed. (default) When "1", the settings can be changed. Note that "0" is output for the INDEX number, elapsed time within a movement, and absolute time while DLD = 1. The control, address and movement number settings can be changed regardless of the DLD setting. - 71 - CXD3048R $A9E commands (preset: $A9E00000) Command A9E (DRAM I/F) Data 1 D3 1 D2 0 D1 0 D0 1 D3 1 Data 2 D2 1 D1 1 D0 0 D3 1 Data 3 D2 D1 D0 0 D3 Data 4 D2 D1 D0 DRWR DRADR DRD15 DRD14 DRD13 DRD12 Data 5 D3 D2 D1 D0 D3 Data 6 D2 D1 D0 D3 Data 7 D2 D1 D0 DRD11 DRD10 DRD9 DRD8 DRD7 DRD6 DRD5 DRD4 DRD3 DRD2 DRD1 DRD0 DRWR: This bit sets write/read for access from the microcomputer to the DRAM. When "0", the read from DRAM mode is set. (default) When "1", the write to DRAM mode is set. DRADR: This bit sets the address control method for access from the microcomputer to the DRAM. When "0", relative address control is set. (default) When "1", absolute address control is set. DRD15 to DRD0: These bits set the data to be written to the DRAM for access from the microcomputer to the DRAM. $A9F commands (preset: $A9F00000) Command A9F (DRAM I/F) Data 1 D3 1 D2 0 D1 0 D0 1 D3 1 Data 2 D2 1 D1 1 D0 1 D3 Data 3 D2 D1 D0 D3 Data 4 D2 D1 D0 DADR DADR DADR DADR DADR DADR DADR DADR 15 14 13 12 19 18 17 16 Data 6 Data 7 D0 D3 D2 D1 D0 Data 5 D3 D2 D1 D0 D3 D2 D1 DADR DADR DADR DADR DADR DADR DADR DADR DADR DADR DADR DADR 11 10 9 8 7 6 5 4 3 2 1 0 DADR19 to DADR0: These bits set the DRAM address for access from the microcomputer to the DRAM. - 72 - CXD3048R $AA commands (preset: $AA00004) Command AA (Compression setting) Data 1 D3 1 D2 0 D1 1 D0 0 D3 Data 2 D2 D1 D0 0 D3 ADP WO Data 3 D2 0 D1 0 D0 0 D3 0 Data 4 D2 GR SEL D1 0 D0 0 ADP BIT BIT ON SL1 SL0 Data 5 D3 D2 D1 0 D0 0 D3 0 Data 6 D2 ORMU D1 0 D0 0 ADPCM ADPCM SEL MUTE ADPON: This bit sets audio data compressed/uncompressed. When "0", the audio data uses uncompressed mode. (default) When "1", the audio mode is compressed mode. BITSL1, BITSL0: These bits set the audio data compression mode. BITSL1 0 0 1 BITSL0 0 1 0 Compression mode 4 bits 6 bits 8 bits : preset The CD-DSP block LRCK and shock-proof memory controller block LRCK are resynchronized. This command should be used when the read speed is changed by $A7 commands READ2, READS2 and READS1. When "0", not resynchronized. (default) When "1", resynchronized. Note) * Set the $AD command CDDSP SLEEP to 0 for resynchronization. * ADPWO should be returned to "0" after ADPWO is set to "1" and one or more LRCK cycle of CD-DSP block is waited. GRSEL: This bit selects the GRSCOR signal output. Note that GRSCOR is output from the WDCK pin when $8 command SCOR SEL = 1. When "0", the GRSCOR signal is output at the timing used inside the shock-proof memory controller block. (default) When "1", the GRSCOR signal generated by the CD DSP block is output. ADPCM SEL: This bit selects ADPCM compensation. When "0", ADPCM is not compensated. When "1", ADPCM is compensated. ADPCM MUTE: This bit sets mute at ADPCM compensation. When "0", it does not mute at ADPCM compensation. When "1", it mutes at ADPCM compensation. ORMU: This bit controls the output signal from the LRMU pin. When "0", the "0" detection flag for Lch and Rch (AND output) is output. When "1", the OR output is made with the "0" detection flag for Lch and Rch (AND output) and SYSM. ADPWO: - 73 - CXD3048R $AB commands (preset: $AB000000) Command AB (EFM playability enhancement setting) Data 1 D3 1 D2 0 D1 1 D0 1 D3 ARD TEN Data 2 D2 1 D1 1 D0 1 D3 1 Data 3 D2 0 D1 1 D0 0 D3 0 Data 4 D2 0 D1 1 D0 0 Data 5 D3 1 D2 0 D1 0 D0 0 D3 0 Data 6 D2 0 D1 0 D0 0 D3 1 Data 7 D2 0 D1 0 D0 0 ARDTEN: This is the EFM playability enhancement setting. When "0", the EFM playability enhancement function is off. When "1", the EFM playability enhancement function is on. Set this command in the condition when a disc is not being played back. - 74 - CXD3048R $AC commands (preset: $AC0C001) Command AC (Sync expansion specification) Data 1 D3 1 D2 1 D1 0 D0 0 D3 AVW Data 2 D2 0 D1 D0 D3 Data 3 D2 D1 D0 D3 0 Data 4 D2 0 D1 0 D0 0 SFP5 SFP4 SFP3 SFP2 SFP1 SFP0 Data 5 D3 D2 D1 D0 D3 Data 6 D2 D1 D0 REF SLIM SLIM OV4 OV3 OV2 OV1 OV0 SEL2 1 0 AVW: This bit sets the sync protection window width automatic expansion function. When "0", the sync protection window width automatic expansion function is off. When "1", the sync protection window width automatic expansion function is on. This setting is not affected by the sync forward protection times setting SFP5 to SFP0. The sync protection window width (6 channel clocks when WSEL = 0, 26 channel clocks when WSEL = 1) is widened 32 channel clocks at a time each time a sync mark is inserted during the interval from the 16th forward protection until GFS goes high. When the maximum window width is reached (when the window width exceeds 588 channel clocks), GTOP goes high. These bits set the frame sync forward protection times. The setting range is from 1 to 3F (h). For details on frame sync protection, see "4-2. Frame Sync Protection". Part of this command bit register is also used by $C SFP3 to SFP0. Of $AC SFP3 to SFP0 or $C SFP3 to SFP0, the command bit setting made last is valid. When using an existing status, set the value with $C SFP5 to SFP0. When using the $AC commands, set $AC SFP3 to SFP0 to the value set by $C SFP3 to SFP0. This bit sets the refresh rate to DRAM. See the description of $A7 command REFSEL. This bit sets the DRAM write speed limit value. SLIM1 0 0 1 1 SLIM0 0 1 0 1 Write speed limit value Up to 4.0x speed write Up to 4.5x speed write Up to 5.0x speed write Up to 5.5x speed write SFP5 to SFP0: REFSEL2: SLIM1, 0: OV4 to OV0: : preset Note) This command is valid when $A7X XWIH2 = 1. This bit sets the limit value of the speed violation number for one GRSCOR which is reflected to XWIH. OV4 to OV0 00000 to 11111 Limit value of speed violation number Can be set from 1 to 31 times. : Preset value: 00001 Note) * The violation speed is set with the $AC commands SLIM 1 and 0. * This command is valid when $A7X XWIH2 = 1. - 75 - CXD3048R $AD commands (preset: $AD040) Command AD (Sleep setting) ADCPS: Data 1 D3 1 D2 1 D1 0 D0 1 D3 ADCPS Data 2 D2 D1 D0 D3 Data 3 D2 D1 D0 D3 Data 4 D2 D1 D0 0 HCAV ERCNT DSP DSSP ASYM ESP LPF DSUB ASEQ PCOL SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP This bit sets the operating mode of the DSSP block A/D converter. When "0", the operating mode of the DSSP block A/D converter is set to normal. (default) When "1", the operating mode of the DSSP block A/D converter is set to power saving. DSP SLEEP: This bit sets the operating mode of the DSP block. When "0", the DSP block operates normally. (default) When "1", the DSP block clock is stopped. This makes it possible to reduce power consumption. DSSP SLEEP: This bit sets the operating mode of the DSSP block. When "0", the DSSP block operates normally. (default) When "1", the DSSP block clock is stopped. In addition, the A/D converter and operational amplifier in the DSSP block are set to standby mode. This makes it possible to reduce power consumption. ASYM SLEEP: This bit sets the operating mode of the asymmetry correction circuit and VCO1/VCO2. When "0", the asymmetry correction circuit and VCO1/VCO2 operate normally. (default) When "1", the operational amplifier in the asymmetry correction circuit is set to standby mode. In addition, the multiplier PLL VCO1 and wide-band PLL VCO2 oscillation are stopped. This makes it possible to reduce power consumption. ESP SLEEP: This bit sets the operating mode of the shock-proof memory controller block. When "0", the shock-proof memory controller block operates normally. (default) When "1", the shock-proof memory controller block clock is stopped. This makes it possible to reduce power consumption. LPF SLEEP: This bit sets the operating mode of the analog low-pass filter block. When "0", the analog low-pass filter block operates normally. When "1", the analog low-pass filter block is set to standby mode. (default) This makes it possible to reduce power consumption. DSUB SLEEP: This bit sets the operating mode of the Ubit generation block inside the DOUT generation circuit in the DAC block. This setting has no effect on the DOUT generation circuit in the CD DSP block. When "0", the Ubit generation block operates normally. (default) When "1", The clock for the Ubit generation block inside the DOUT generation circuit in the DAC block is stopped. This makes it possible to reduce power consumption. Also, in this case Ubit is set to "0". ASEQ SLEEP: This bit sets the operation mode of the servo auto sequencer block. When "0", the servo auto sequencer operates normally. (default) When "1", the servo auto sequencer block clock is stopped. This makes the power consumption to be reduced. PCOL: The PCOL pin in DSP sleep mode is fixed to low. When "0", the PCO pin gradually becomes low by the external filter time constant. (default) When "1", the PCO pin digitally becomes low. Note) Set DSP SLEEP to "1" so that DSP sleep mode is entered. HCAV SLEEP: This bit sets the hard CAV block operation mode. When "0", the hard CAV block operates normally. (default) When "1", the hard CAV block clock is stopped. This makes the power consumption to be reduced. ERCNT SLEEP: This bit sets operation mode for the error rate counter block. When "0", normally operates. (default) When "1", the clock in the error rate counter block stops. This reduces the power consumption. The DAC block clock can be stopped by setting $A5 command PWDN (when Data 2 D3 = 0, D2 = 1). - 76 - CXD3048R $AE commands (preset: $AE0) Command AE (Variable pitch setting) Data 1 D3 1 D2 1 D1 1 D0 0 D3 Data 2 D2 D1 D0 D3 Data 3 D2 D1 D0 D3 Data 4 D2 D1 D0 VARI VARI WTC SCSY SENS SENS SENS SENS ON USE C2PO (sub) SEL3 SEL2 SEL1 SEL0 Processing Command bit VARION = 0 VARION = 1 Command bit VARIUSE = 0 VARIUSE = 1 Variable pitch mode is off. (The internal clock uses the crystal reference.) Variable pitch mode is on. (The internal clock uses the VCO2 reference.) Processing Set VARIUSE = 0 when not using variable pitch mode. Set VARIUSE = 1 when using variable pitch mode. See "$DX commands" for the variable pitch range and example of use. WTC C2PO: This bit selects the write prohibit factor to DRAM. When "0", write prohibition is not allowed by the C2PO error number or external input. When "1", write prohibition is allowed by the C2PO error number or external input. Use this command only when $8 CDROM = 0. * Use this command in conjunction with the $AX command A11 SEL and $A4 commands max C2PO7 to max C2PO0. This bit sets the GRSCOR resynchronization period. See the $8X command SCSY. (Set the $8X command to "0" when using this bit.) SCSY (sub): SENS SEL3 to SENS SEL0: SENS SENS SENS SENS SEL3 SEL2 SEL1 SEL0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 SOC2 0 1 1 1 1 1 1 1 1 SDTO TEXT SOCT SOCT XSOE XSOE OUT OUT 1 0 0 02 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SENS switching SENS serial data Subcode Q Various signals Error rate CD-TEXT Shock-proof memory controller status Special area read Special area status VF0 to VF9 - 77 - CXD3048R $AF commands (preset: $AF8000) Command AF (Spindle servo setting) Data 1 D3 1 D2 1 D1 1 D0 1 D3 Data 2 D2 D1 D0 D3 Data 3 D2 D1 D0 0 D3 Data 4 D2 D1 0 D0 MDP CTL4 SYG3 SYG2 SYG1 SYG0 MDP MDP LPWR2 EA EA EA EA OUTSL1 OUTSL0 MDS MDP CTL UP Data 5 D3 D2 D1 D0 MDP MDP MDP MDP CTL3 CTL2 CTL1 CTL0 SYG3EA to SYG0EA: These bits set the spindle drive output gain. However, this is valid only in CLV-N mode. SYG3EA SYG2EA SYG1EA SYG0EA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 : preset MDP OUTSL1, MDP OUTSL0: These bits set the spindle drive output method. MDP OUTSL1 0 1 0 MDP OUTSL0 0 0 1 Spindle drive output Ternary output from the MDP pin Binary output from the MDS and MDP pins Command-based MDP and MDS output control : preset - 78 - GAIN 0 (- dB) 0.125 (-18.1dB) 0.250 (-12.0dB) 0.375 (-8.5dB) 0.500 (-6.0dB) 0.625 (-4.1dB) 0.750 (-2.5dB) 0.875 (-1.2dB) 1.000 (0.0dB) 1.125 (+1.0dB) 1.250 (+1.9dB) 1.375 (+2.8dB) 1.500 (+3.5dB) 1.625 (+4.2dB) 1.750 (+4.9dB) 1.875 (+5.5dB) CXD3048R The low output (brake pulse) of the MDP pin can be masked. When "0", binary output is high or low output, and ternary output is high, low or high impedance output. (default) When "1", high or high impedance is output. This makes it possible to mask the brake pulse. MDS CTL: This bit sets the PWM output polarity according to the setting from the microcomputer. (valid when MDP OUTSL1 = 0 and MDP OUTSL0 = 1) When "0", the MDS pin output is set low. When "1", the MDS pin output is set high. MDP UP: This bit switches the MDP pin according to the setting from the microcomputer. (valid when MDP OUTSL1 = 0 and MDP OUTSL0 = 1) When "0", the MDP pin output is set to PWM output. When "1", the MDP pin output is set high. MDP CTL4 to MDP CTL0: These bits set the PWM output value according to the setting from the microcomputer. (valid when MDP OUTSL1 = 0 and MDP OUTSL0 = 1) The carrier frequency is 176.4kHz. (88.2kHz when set to quasi-double speed) At the minimum value (MDP CTL4 to MDP CTL0 = 0), the MDP pin output is set low. At the maximum value (MDP CTL4 to MDP CTL0 = 1F (h)), the MDP pin output is set high for 31/32 intervals. Note that when $AF command MDP UP = 1, the MDP pin output is set high regardless of the MDP CTL4 to MDP CTL0 setting value. Command-based MDP and MDS output control (MDP OUTSL1 = 0, MDP OUTSL0 = 1) (1) Timing Chart 1 LPWR2 = 0, MDP UP = 0, MDP CTL4 to MDP CTL0 = 10 (h) 5.67s (176kHz) LPWR2: MDP The MDP waveform ratio is set by MDP CTL4 to MDP CTL0. When MDP CTL4 to MDP CTL0 = 10 (h), 10 (h)/20 (h) intervals are high. (2) Timing Chart 2 LPWR2 = 0, MDP UP = 1, MDP CTL4 to MDP CTL0 = 10 (h) H MDP When MDP UP = 1, MDP is fixed high regardless of MDP CTL4 to MDP CTL0. (3) Timing Chart 3 MDP LPWR2 = 1, MDP UP = 0, MDP CTL4 to MDP CTL0 = 10 (h) Z When LPWR2 = 1, the low output of MDP binary output becomes high impedance. - 79 - CXD3048R $BX commands This command sets the traverse monitor count. Command Traverse monitor count setting Data 1 D3 D2 D1 D0 D3 Data 2 D2 D1 29 D0 28 D3 27 Data 3 D2 26 D1 25 D0 24 D3 23 Data 4 D2 22 D1 21 D0 20 215 214 213 212 211 210 * When the set number of tracks are counted during fine search, the sled control for the traverse cycle control goes off. * The traverse monitor count is set to monitor the traverse status using the SENS outputs COMP and COUT. The monitor output is set as follows. Command Traverse monitor count setting Data 5 D3 0 D2 0 D1 D0 D3 Data 6 D2 MD2 D1 0 D0 0 MTSL1 MTSL0 ASYE Command bit MTSL1 0 0 1 1 MTSL0 0 1 0 1 XUGF MINT0 RFCK C4M Output data XPCK MNT1 XPCK FSTO GFS MNT2 XROF GFS : preset However, the $39 command SRO1 and $A7 command MON SEL must be set to "0". C2PO MNT3 GTOP C2PO Command bit ASYE = 1 ASYE = 0 Asymmentry is on. Asymmentry is off. Processing : preset Command bit MD2 = 0 MD2 = 1 Processing Digital Out on/off control. Off when "0". Digital Out on/off control. On when "1". : preset - 80 - CXD3048R $CX commands Command Data 1 D3 D2 D1 D0 D3 Data 2 D2 D1 D0 Gain Gain Gain Gain Gain Gain Spindle servo PCC1 PCC0 coefficient setting MDP1 MDP0 MDS1 MDS0 DCLV1 DCLV0 CLV CTRL ($DX) Gain CLVS * CLVS mode gain setting: GCLVS Gain MDS1 0 0 0 0 1 1 Gain MDS0 0 0 1 1 0 0 Gain CLVS 0 1 0 1 0 1 GCLVS -12dB -6dB -6dB 0dB 0dB +6dB * CLVP mode gain setting: GMDP: GMDS Gain MDP1 0 0 1 Gain MDP0 0 1 0 GMDP -6dB 0dB +6dB Gain MDS1 0 0 1 Gain MDS0 0 1 0 GMDS -6dB 0dB +6dB * DCLV overall gain setting: GDCLV Gain DCLV1 0 0 1 Gain DCLV0 0 1 0 GDCLV 0dB +6dB +12dB Command bit PCC1 0 0 1 1 PCC0 0 1 0 1 The VPCO signal is output. The VPCO pin output is high impedance. The VPCO pin output is low. The VPCO pin output is high. Processing * This command controls the VPCO pin signal. The VPCO output can be controlled with this setting. - 81 - CXD3048R Command Data 3 D3 D2 D1 D0 D3 Data 4 D2 D1 D0 Spindle servo SFP3 coefficient setting Command bit SFP3 to SFP0 Command bit SRP3 to SRP0 SFP2 SFP1 SFP0 SRP3 SRP2 SRP1 SRP0 Processing Sets the number of frame sync forward protection times. The setting range is from 1 to F (h). Processing Sets the number of frame sync backward protection times. The setting range is from 1 to F (h). See "4-2. Frame Sync Protection" regarding frame sync protection. * The CXD3048R can serially output the 40 bits (10 BCD codes) of error rate data selected by EDC7 to EDC0 from the SQSO pin and monitor this data using a microcomputer. In order to output error rate data, set $C commands for C1 and C2 individually, and set $8 commands SOCT0 and SOCT1 to "1". Then, the data can be read out from the SQSO pin by sending 40 SQCK pulses. Command Data 5 D3 D2 D1 D0 D3 Data 6 D2 D1 D0 Spindle servo EDC7 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 coefficient setting Preset value: 00h Error rate monitor commands Command bit EDC7 = 0 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 EDC7 = 1 EDC6 EDC5 EDC4 EDC3 EDC2 EDC1 EDC0 Prpcessing The [No C1 errors, pointer reset] count is output When "1". The [One C1 error corrected, pointer reset] count is output When "1". The [No C1 errors, pointer set] count is output When "1". The [One C1 error corrected, pointer set] count is output When "1". The [Two C1 errors corrected, pointer set] count is output When "1". The [C1 correction impossible, pointer set] count is output When "1". 7350-frame count cycle mode1 When "0". 73500-frame count cycle mode2 When "1". The [No C2 errors, pointer reset] count is output When "1". The [One C2 error corrected, pointer reset] count is output When "1". The [Two C2 errors corrected, pointer reset] count is output When "1". The [Three C2 errors corrected, pointer reset] count is output When "1". The [Four C2 errors corrected, pointer reset] count is output When "1". The [C2 correction impossible, pointer copy] count is output When "1". The [C2 correction impossible, pointer set] count is output When "1". 1 The values selected by C1 (EDC1 to EDC6) and C2 (EDC0 to EDC6) are added to C1 and C2, respectively, and output every 7350 frames. 2 The values selected by C1 (EDC1 to EDC6) and C2 (EDC0 to EDC6) are added to C1 and C2, respectively, and output every 73500 frames. - 82 - CXD3048R $DX commands Command CLV CTRL Data 1 D3 0 D2 TB D1 TP D0 Gain CLVS See "$CX commands". Command bit TB = 0 TB = 1 TP = 0 TP = 1 Description Bottom hold at a cycle of RFCK/32 in CLVS mode. Bottom hold at a cycle of RFCK/16 in CLVS mode. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode. Command CLV CTRL Data 2 D3 VP7 D2 VP6 D1 VP5 D0 VP4 D3 VP3 Data 3 D2 VP2 D1 VP1 D0 VP0 D3 Data 4 D2 D1 0 D0 0 VP VP CTL1 CTL0 The settings in CAV-W mode are as follows. Command bit VP0 to VP7 Sets the spindle rotational velocity. Processing Command bit VPCTL1 0 0 1 1 VPCTL0 0 1 0 1 Processing The setting of VP0 to VP7 is multiplied by 1. The setting of VP0 to VP7 is multiplied by 2. The setting of VP0 to VP7 is multiplied by 3. The setting of VP0 to VP7 is multiplied by 4. The above setting should be "0", "0" except for the CAV-W operating mode. - 83 - CXD3048R The rotational velocity R of the spindle can be expressed with the following equation. R= 256 - n xl 32 R: Relative velocity at normal speed = 1 n: VP0 to VP7 setting value l: Multiple set by VPCTL0, VPCTL1 Description Playback at half (normal) speed to Playback at normal (double) speed to Playback at (quadruple) speed Command bit VP0 to VP7 = F0 (h) : VP0 to VP7 = E0 (h) : VP0 to VP7 = C0 (h) Notes) 1. Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high. 2. Values in parentheses are for when DSPB is "1". 4 R - Relative velocity [multiple] 3.5 3 2.5 2 1.5 1 0.5 P DS B= 1 DSPB =0 F0 E0 VP0 to VP7 setting value [h] D0 C0 - 84 - CXD3048R The settings in variable pitch mode are as follows. Command bit Processing VPCTL1 to VPCTL0, Sets the pitch for variable pitch mode. VP7 to VP0 The pitch setting can be expressed with the following equation. P= -n 10 [%] P: Pitch setting value n: VPCTL1 and VPCTL0, VP7 to VP0 setting value (two's complement, VPCTL1 = sign bit) Command setting example $D60080 : $D6FF80 $D600C0 : $D6FFC0 $D60000 : $D6FF00 $D60040 : $D6E740 Command bit VPCTL1 1 VPCTL0 0 VP7 to VP0 00 (H) -- FF (H) 00 (H) 1 1 -- FF (H) 00 (H) 0 0 -- FF (H) 00 (H) 0 1 -- E7 (H) Pitch setting value [%] +51.2 to +25.7 +25.6 to +0.1 0.0 to -25.5 -25.6 to -48.7 The pitch setting range is from -48.7 to +51.2%. The plus pitch setting should not exceed the playback speed given in the Recommended Operating Conditions. An example of variable pitch mode commands is shown below. $EX001 (Sets INV VPCO = 1.) $AE4 (Setting to enable variable pitch mode.) $AEC (Turns on variable pitch mode. The internal clock uses the VCO2 reference.) $D60A00 (Sets the pitch to -1.0%.) $D60000 (Sets the pitch to 0.0%.) $AE4 (Turns off variable pitch mode. The internal clock uses the crystal reference.) - 85 - CXD3048R $EX commands Data 1 Command SPD mode D3 CM3 D2 CM2 D1 CM1 D0 D3 Data 2 D2 D1 D0 D3 Data 3 D2 D1 D0 CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON Command bit CM3 0 1 1 1 1 0 CM2 0 0 0 1 1 1 CM1 0 0 1 1 1 1 CM0 0 0 0 0 1 0 Mode STOP KICK BRAKE CLVS CLVP CLVA Spindle stop mode.1 Spindle forward rotation mode.1 Spindle reverse rotation mode. Valid only when LPWR = 0 in any mode.1 Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RFPLL capture range. PLL servo mode. Automatic CLVS/CLVP switching mode. Used for normal playback. Description 1 See Timing Charts 1-6 to 1-29. In the digital CLV servo, the sampling frequency of the internal digital filter is switched simultaneously with the switching of CLVP/CLVS. Then, the CLVS mode cut-off frequency fc is 70Hz when $D command TB = 0 or 140Hz when $D command TB = 1. Spindle control can be set to the ternary output of only MDP or the binary outputs of MDP and MDS by $AF commands MDPOUTSL1 and MDPOUTSL0. Command bit EPWM SPDC 0 0 0 0 1 0 0 0 0 1 0 0 ICAP 0 0 0 1 1 0 SFSL 0 0 0 0 0 0 VC2C 0 0 1 0 0 0 HIFC 0 0 1 1 1 1 LPWR VPON 0 0 0 0 0 0 0 0 0 1 1 1 INV VPCO 0 1 0 0 0 1 Mode Description Crystal reference CLV servo. VCO2 reference CLV servo. Used for playback in CLV-W mode.2 Spindle control with VP0 to VP7. Spindle control with the external PWM. VCO control3 CLV-N CLV-N CLV-W CAV-W CAV-W VCO-C 2 Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode. 3 Fig. 3-3 shows the control flow with the microcomputer software in VCO-C mode. - 86 - CXD3048R Mode LPWR LPWR2 Command KICK Timing chart - Ternary output 1-6 (a) 1-6 (b) 1-6 (c) 1-7 (a) 1-7 (b) 1-7 (c) 1-8 (a) 1-8 (b) 1-8 (c) 1-9 (a) 1-9 (b) 1-9 (c) 1-10 (a) 1-10 (b) 1-10 (c) Timing chart - Binary output 1-18 (a) 1-18 (b) 1-18 (c) 1-19 (a) 1-19 (b) 1-19 (c) 1-20 (a) 1-20 (b) 1-20 (c) 1-21 (a) 1-21 (b) 1-21 (c) 1-22 (a) 1-22 (b) 1-22 (c) CLV-N 0 0 BRAKE STOP KICK 0 CLV-W 1 0 BRAKE STOP KICK 0 BRAKE STOP KICK 0 CAV-W 1 0 BRAKE STOP KICK 0 BRAKE STOP Mode CLV-N CLV-W LPWR 0 0 1 0 1 0 1 LPWR2 0 0 Timing chart - Ternary output 1-11 1-12 1-13 1-14 (EPWM = 0) 1-15 (EPWM = 0) 1-16 (EPWM = 1) 1-17 (EPWM = 1) Timing chart - Binary output 1-23 1-24 1-25 1-26 (EPWM = 0) 1-27 (EPWM = 0) 1-28 (EPWM = 1) 1-29 (EPWM = 1) CAV-W 0 - 87 - CXD3048R Mode LPWR LPWR2 Command KICK Timing chart - Ternary output 1-8 (a) 1-8 (b) 1-8 (c) 1-8 (a) 1-8 (b) 1-8 (c) 1-10 (a) 1-10 (b) 1-10 (c) 1-10 (a) 1-10 (b) 1-10 (c) Timing chart - Binary output 1-30 (a) 1-30 (b) 1-30 (c) 1-31 (a) 1-31 (b) 1-31 (c) 1-32 (a) 1-32 (b) 1-32 (c) 1-33 (a) 1-33 (b) 1-33 (c) 0 CLV-W 1 1 BRAKE STOP KICK 1 BRAKE STOP KICK 0 CAV-W 1 1 BRAKE STOP KICK 1 BRAKE STOP Mode CLV-W LPWR 0 1 0 1 0 1 LPWR2 1 Timing chart - Ternary output 1-13 1-13 1-15 (EPWM = 0) 1-15 (EPWM = 0) 1-17 (EPWM = 1) 1-17 (EPWM = 1) Timing chart - Binary output 1-34 1-35 1-36 (EPWM = 0) 1-37 (EPWM = 0) 1-38 (EPWM = 1) 1-39 (EPWM = 1) CAV-W 1 Command SPD mode Data 4 D3 Gain CAV1 D2 Gain CAV0 D1 0 D0 INV VPCO See page 86. Gain CAV1 0 0 1 1 Gain CAV0 0 1 0 1 Gain 0dB -6dB -12dB -18dB * This sets the gain when controlling the spindle with VP7 to VP0 in CAV-W mode. Note) The Gain CAV1 and Gain CAV0 commands are invalid for spindle control with the external PWM. - 88 - Timing Chart 1-3 LRCK 48 bit slot WDCK CDROM = 0 C2PO Rch 16-bit C2 Pointer Lch 16-bit C2 Pointer If C2 Pointer = 1, data is NG - 89 - CDROM = 1 C2PO C2 Pointer for upper 8 bits C2 Pointer for lower 8 bits C2 Pointer for upper 8 bits C2 Pointer for lower 8 bits Rch C2 Pointer Lch C2 Pointer CXD3048R Timing Chart 1-4 750ns to 120s 1 SQCK 2 3 80 81 96 SQSO CRCF Subcode Q data See "Subcode Interface" D0 D1 D2 D3 D4 D5 D6 D13 D14 L/R 15-bit peak data Absolute value display, LSB first Peak data L/R flag - 90 - WFCK SQCK SQSO 1 2 3 1 2 3 96 clock pulses 96 clock pulses L/R CRCF R/L CRCF 96-bit data Hold section Peak data of this section 16 bits Level Meter Timing CXD3048R Timing Chart 1-5 1 WFCK 2 3 1 2 3 96 clock pulses SQCK 96 clock pulses - 91 - CRCF Measurement CRCF Measurement CRCF Measurement Peak Meter Timing CXD3048R CXD3048R Ternary output from MDP pin ($AF MDPOUTSL1 = 0, MDPOUTSL0 = 0) Timing Chart 1-6 CLV-N mode LPWR = 0, LPWR2 = 0 KICK H Z (a) KICK Z L (b) BRAKE BRAKE STOP MDP MDP MDP Z (c) STOP Timing Chart 1-7 CLV-W mode (when following the spindle rotational velocity) LPWR = 0, LPWR2 = 0 KICK H Z (a) KICK Z L (b) BRAKE BRAKE STOP MDP MDP MDP Z (c) STOP Timing Chart 1-8 CLV-W mode (when following the spindle rotational velocity) LPWR = 1, LPWR2 = 0 KICK H Z (a) KICK (b) BRAKE (c) STOP BRAKE STOP MDP MDP Z MDP Z Timing Chart 1-9 CAV-W mode LPWR = 0, LPWR2 = 0 KICK H BRAKE STOP MDP MDP L (b) BRAKE MDP Z (a) KICK (c) STOP Timing Chart 1-10 CAV-W mode LPWR = 1, LPWR2 = 0 KICK H BRAKE STOP MDP MDP Z (b) BRAKE MDP Z (c) STOP (a) KICK - 92 - CXD3048R Timing Chart 1-11 CLV-N mode LPWR = 0, LPWR2 = 0 n * 236 (ns) n = 0 to 31 Acceleration MDP Z Deceleration 132kHz 7.6s Timing Chart 1-12 CLV-W mode LPWR = 0, LPWR2 = 0 Acceleration MDP Z Deceleration 264kHz 3.8s Timing Chart 1-13 CLV-W mode LPWR = 1, LPWR2 = 0 Acceleration MDP Z 264kHz 3.8s The BRAKE pulse is masked when LPWR = 1. Timing Chart 1-14 CAV-W mode EPWM = LPWR = 0, LPWR2 = 0 Acceleration MDP Z Deceleration 264kHz 3.8s Timing Chart 1-15 CAV-W mode EPWM = 0, LPWR = 1, LPWR2 = 0 Acceleration MDP Z 264kHz 3.8s The BRAKE pulse is masked when LPWR = 1. - 93 - CXD3048R Timing Chart 1-16 CAV-W mode EPWM = 1, LPWR = 0, LPWR2 = 0 H PWMI L H MDP L Acceleration Deceleration Timing Chart 1-17 CAV-W mode EPWM = LPWR = 1, LPWR2 = 0 H PWMI L H MDP Z Acceleration The BRAKE pulse is masked when LPWR = 1. Binary output from MDP and MDS pins ($AF MDPOUTSL1 = 1, MDPOUTSL0 = 0) Timing Chart 1-18 CLV-N mode LPWR = 0, LPWR2 = 0 KICK H MDS MDS L MDS BRAKE STOP MDP H MDP L (a) KICK H MDP L (b) BRAKE L (c) STOP Timing Chart 1-19 CLV-W mode (when following the spindle rotational velocity) LPWR = 0, LPWR2 = 0 KICK H MDS MDS L MDS BRAKE STOP MDP H MDP L (a) KICK H MDP L (b) BRAKE L (c) STOP - 94 - CXD3048R Timing Chart 1-20 CLV-W mode (when following the spindle rotational velocity) LPWR = 1, LPWR2 = 0 KICK H MDS MDS MDS BRAKE STOP MDP H MDP L L MDP L Timing Chart 1-21 CAV-W mode LPWR = 0, LPWR2 = 0 KICK H BRAKE STOP MDS MDS L MDS MDP H MDP H MDP L (a) KICK (b) BRAKE (c) STOP Timing Chart 1-22 CAV-W mode LPWR = 1, LPWR2 = 0 KICK H MDS MDS MDS BRAKE STOP MDP H MDP L (b) BRAKE MDP L (c) STOP (a) KICK - 95 - CXD3048R Timing Chart 1-23 CLV-N mode LPWR = 0, LPWR2 = 0 MDS L Acceleration MDP 132kHz 7.6s Output waveforms with DCLV = 1 n * 236 (ns) n = 0 to 31 Deceleration H Timing Chart 1-24 CLV-W mode LPWR = 0, LPWR2 = 0 MDS L Acceleration MDP Deceleration L 264kHz 3.8s Output waveforms with DCLV = 1 Timing Chart 1-25 CLV-W mode LPWR = 1, LPWR2 = 0 MDS H Acceleration MDP L 264kHz 3.8s Output waveforms with DCLV = 1 The BRAKE pulse is masked when LPWR = 1. Timing Chart 1-26 CAV-W mode EPWM = 0, LPWR = 0, LPWR2 = 0 Acceleration MDP Deceleration L 264kHz 3.8s MDS L - 96 - CXD3048R Timing Chart 1-27 CAV-W mode EPWM = 0, LPWR=1, LPWR2 = 0 Acceleration MDP L 264kHz 3.8s The BRAKE pulse is masked when LPWR = 1. H MDS Timing Chart 1-28 CAV-W mode EPWM = 1, LPWR = 0, LPWR2 = 0 H PWMI L H MDS L Deceleration H MDP Acceleration Timing Chart 1-29 CAV-W mode EPWM = 1, LPWR = 1, LPWR2 = 0 H PWMI L H MDS H MDP Acceleration - 97 - CXD3048R Timing Chart 1-30 CLV-W mode (when following the spindle rotational velocity) LPWR = 0, LPWR2 = 1 KICK H MDS MDS L MDS BRAKE STOP MDP H Z MDP H Z MDP Z (a) KICK (b) BRAKE (c) STOP Timing Chart 1-31 CLV-W mode (when following the spindle rotational velocity) LPWR = 1, LPWR2 = 1 KICK H MDS MDS MDS BRAKE STOP MDP H Z (a) KICK MDP Z (b) BRAKE MDP Z (c) STOP Timing Chart 1-32 CAV-W mode LPWR = 0, LPWR2 = 1 KICK H BRAKE STOP MDS MDS L MDS MDP H MDP H MDP Z (a) KICK (b) BRAKE (c) STOP Timing Chart 1-33 CAV-W mode LPWR = 1, LPWR2 = 1 KICK H MDS MDS MDS BRAKE STOP MDP H MDP Z (b) BRAKE MDP Z (c) STOP (a) KICK - 98 - CXD3048R Timing Chart 1-34 CLV-W mode LPWR = 0, LPWR2 = 1 MDS Acceleration MDP Deceleration Z 264kHz 3.8s Output waveforms with DCLV = 1 Timing Chart 1-35 CLV-W mode LPWR = 1, LPWR2 = 1 MDS H Acceleration MDP Z 264kHz 3.8s Output waveforms with DCLV = 1 The BRAKE pulse is masked when LPWR = 1. Timing Chart 1-36 CAV-W mode EPWM = 0, LPWR = 0, LPWR2 = 1 Acceleration MDP Deceleration Z 264kHz 3.8s MDS L - 99 - CXD3048R Timing Chart 1-37 CAV-W mode EPWM = 0, LPWR=1, LPWR2 = 1 Acceleration MDP Z 264kHz 3.8s The BRAKE pulse is masked when LPWR = 1. H MDS Timing Chart 1-38 CAV-W mode EPWM = 1, LPWR = 0, LPWR2 = 1 H PWMI L H MDS L Deceleration H MDP Acceleration Timing Chart 1-39 CAV-W mode EPWM = 1, LPWR = 1, LPWR2 = 1 H PWMI L H MDS H MDP Z Acceleration - 100 - CXD3048R [2] Subcode Interface There are two methods for reading out a subcode externally. The 8-bit subcodes P to W can be read out from SBSO by inputting EXCK. The subcode-Q can be read out after checking CRC of the 80 bits in the subcode frame. The subcode-Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high. 2-1. P to W Subcode Readout Data can be read out by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.) 2-2. 80-bit Subcode-Q Readout Fig. 2-2 shows the peripheral block of the 80-bit subcode-Q register. * First, subcode-Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit. * 96-bit subcode-Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are loaded into the parallel/serial register. When SQSO goes high after SCOR is output, the CPU determines that new data (which passed the CRC check) has been loaded. * When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first. * Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low. * The retriggerable monostable multivibrator has a time constant from 270 to 400s. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register. * While the monostable multivibrator is being reset, data cannot be loaded in the peak detection parallel/serial register or the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, these registers will not be rewritten by CRCOK and others. * The previously mentioned peak detection register can be connected to the shift-in of the 80-bit parallel/serial register. For ring control 1, input and output are shorted during peak meter and level meter modes. For ring control 2, input and output are shorted during peak meter mode. This is because the register is reset with each readout in level meter mode, and to prevent readout destruction in peak meter mode. As a result, the 96-bit clock must be input in peak meter mode. * The absolute time after peak is stored in the memory in peak meter mode as noted in "Description of peak meter mode" on page 95. See Timing Chart 2-3. * The clock is input from the SQCK pin to perform these operations. The high and low intervals of the clock should be between 750ns and 120s. - 101 - CXD3048R Timing Chart 2-1 Internal PLL clock 4.3218 MHz WFCK SCOR EXCK 750ns max SBSO S0 * S1 Q R WFCK SCOR EXCK SBSO S0*S1 Q R S T U V W S0*S1 P1 QRSTUVW P1 P2 P3 Same Same Subcode P.Q.R.S.T.U.V.W Read Timing - 102 - Block Diagram 2-2 (AFRAM) SUBQ (ASEC) (AMIN) 80-bit S/P Register ADDRS CTRL SIN ABCDEFGH 8 Order Inversion 8 8 8 8 8 8 8 8 HGFEDCBA SI 80-bit P/S Register SO LD LD LD LD LD LD ABS time load control for peak value SUBQ CRCC Monostable multivibrator SHIFT LD SHIFT LD - 103 - Ring control 1 SQCK LOAD CONTROL SO 16-bit P/S register SI Ring control 2 CRCF Mix SQSO 16 CXD3048R Peak detection Timing Chart 2-3 1 2 3 91 1 92 2 93 3 94 95 96 97 98 WFCK SCOR Determined by mode SQSO CRCF1 80 or 96 Clock SQCK CRCF1 CRCF2 - 104 - SQCK SQSO Register load forbidder Monostable multivibrator (Internal) 750ns to 120s 270 to 400 when SQCK = high. CRCF ADR0 ADR1 ADR2 ADR3 CTL0 CTL1 CTL2 CTL3 300ns max CXD3048R Timing Chart 2-4 Example: $802000 latch Set SQCK high during this interval. XLAT Internal signal latch SQCK 750ns or more SQSO PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 C1F0 C1F1 C1F2 C2F0 C2F1 C2F2 FOK GFS LOCK EMPH ALOCK VF0 VF1 VF2 VF3 VF4 VF5 VF6 VF7 VF8 VF9 Signal PER0 to PER7 FOK GFS Description RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. Focus OK. High when the frame sync and the insertion protection timing match. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. High when the playback disc has emphasis. GFS is sampled at 460Hz; when GFS is high eight consecutive samples, this pin outputs a high signal. If GFS is low eight consecutive samples, this pin outputs low. Used in CAV-W mode. The result obtained by measuring the rotational velocity of the disc. (See Timing Chart 2-5.) VF0 = LSB, VF9 = MSB. C1F0 0 1 0 1 0 1 0 1 Description No C1 errors; C1 pointer reset One C1 error corrected; C1 pointer reset -- -- No C1 errors; C1 pointer set One C1 error corrected; C1 pointer set Two C1 errors corrected; C1 pointer set C1 correction impossible; C1 pointer set C2F2 0 0 0 0 1 1 1 1 C2F1 0 0 1 1 0 0 1 1 C2F0 0 1 0 1 0 1 0 1 Description No C2 errors; C2 pointer reset One C2 error corrected; C2 pointer reset Two C2 errors corrected; C2 pointer reset Three C2 errors corrected; C2 pointer reset Four C2 errors corrected; C2 pointer reset -- C2 correction impossible; C1 pointer copy C2 correction impossible; C2 pointer set CXD3048R - 105 - 0 0 0 0 1 1 1 1 LOCK EMPH ALOCK VF0 to VF9 C1F2 C1F1 0 0 1 1 0 0 1 1 CXD3048R Timing Chart 2-5 Measurement interval (approximately 3.8s) Reference window (132.2kHz) Measurement pulse (V16M/2) Measurement counter Load VF0 to VF9 m The relative velocity of the disc can be obtained with the following equation. R= m+1 (R: Relative velocity, m: Measurement results) 32 VF0 to VF9 is the result obtained by counting V16M/2 pulses while the reference signal (132.2kHz) generated from XTAL (XTAI, XTAO) (384Fs) is high. This value is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). XLAT Set SQCK high during this period. 750ns or more SQCK SQSO "H" or "L" VF0 VF1 VF2 VF3 VF4 VF5 VF6 VF7 VF8 VF9 - 106 - Timing Chart 2-6 XLAT SQCK - 107 - SQSO C1 MSB 19 18 17 16 15 14 13 12 11 10 9 C1 error rate 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C2 error rate 0 7 3 5 0 0 7 3 5 0 CXD3048R CXD3048R [3] Description of Modes This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations for each mode are described below. 3-1. CLV-N Mode This mode is compatible with the CXD2510Q, and operation is the same as for conventional control. The PLL capture range is 150kHz. 3-2. CLV-W Mode This is the wide capture range mode. This mode allows the conventional PLL to follow the rotational velocity of the disc. This rotational following control uses the built-in VCO2. The spindle is the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below. When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is stopped, CAV-W mode should be used. Specifically, first send $E665X to set CAV-W mode and kick the disc, then send $E60CX to set CLV-W mode if ALOCK is high, which can be read out serially from the SQSO pin. CLV-W mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow according to the microcomputer software in CLV-W mode is shown in Fig. 3-2. In CLV-W mode (normal), low power consumption is achieved by setting LPWR high. Control was formerly performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set high, deceleration pulses are not output, thereby achieving low power consumption mode. Note) The capture range for this mode is theoretically up to the signal processing limit. 3-3. CAV-W Mode This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to the desired rotational velocity. The rotational velocity is determined by the VP0 to VP7 setting values or the external PWM. When controlling the spindle with VP0 to VP7, setting CAV-W mode with the $E665X command and controlling VP0 to VP7 with the $DX commands allows the rotational velocity to be varied from low speed to quadruple speed. (See "$DX commands".) When controlling the spindle with the external PWM, the PWMI pin is binary input which becomes KICK during high intervals and BRAKE during low intervals. The microcomputer can know the rotational velocity using the internal master clock frequency as the parameter. With XTAL (XTAI, XTAO) (384Fs) as the reference frequency, the result after measuring the high interval by the internal master clock is output in 10 bits (VP0 to VP9) from the new CPU interface. These measurement results are 31 when the disc is rotating at normal speed or 127 when it is rotating at quadruple speed. These values match those of the 256 - n for control with VP0 to VP7. (See Timing Chart 2-5.) In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc. Note) The capture range for this mode is theoretically up to the signal processing limit. Note) Set FLFC to "1" for this mode - 108 - CXD3048R 3-4. VCO-C Mode This is VCO control mode. In this mode, the oscillation frequency of the internal master clock (VCLK) can be controlled by setting $D commands VP0 to VP7 and VPCTL0, 1. The VCLK oscillation frequency can be expressed by the following equation. VCLK = 1 (256 - n) 32 n: VP0 to VP7 setting value 1: VPCTL0, 1 setting value The VCO1 oscillation frequency is determined by VCLK. The VCO1 frequency can be expressed by the following equation. * When DSPB = 0 VCO1 = VCLK x * When DSPB = 1 VCO1 = VCLK x 49 16 49 24 - 109 - CXD3048R Rotational velocity CAV-W CLVS CLV-W CLVP Operation mode Spindle mode Target speed KICK Time LOCK ALOCK Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode CLV-W Mode CLV-W MODE START KICK $E8000 Mute OFF $A00XXXX CAV-W $E665X (CLVA) NO ALOCK = H ? YES CLV-W $E60CX (CLVA) (WFCK PLL) ALOCK = L ? NO YES Fig. 3-2. CLV-W Mode Flow Chart - 110 - CXD3048R VCO-C Mode Access START R? (How many minutes of absolute time?) What is the playback speed when access ends? n? (Calculate n) Calculate VP0 to VP7. Transfer $E00510 Switch to VCO control mode. EPWM = SPDC = ICAP = SFSL = VC2C = LPWR = 0 HIFC = VPON = 1 Transfer $DX XX Transfer VP0 to VP7. ( corresponds to VP0 to VP7.) Track Jump Subroutine Switch to normal-speed playback mode. EPWM = SFSL = VC2C = LPWR = 0 SPDC = ICAP = HIFC = VPON = 1 Transfer $E66500 Access END Fig. 3-3. Access Flow Chart Using VCO Control - 111 - CXD3048R [4] Description of other functions 4-1. Channel Clock Recovery by Digital PLL Circuit * The channel clock is necessary for demodulating the EFM signal regenerated by the optical system. Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, a PLL is necessary to recover the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses. The block diagram of this PLL is shown in Fig. 4-1. The CXD3048R has a built-in three-stage PLL. * The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary. The output of this first-stage PLL is used as a reference for all clocks within the LSI. * The second-stage PLL generates the high-frequency clock needed by the third-stage digital PLL. * The third-stage PLL is a digital PLL that recovers the actual channel clock. * The digital PLL in CLV-N mode has a secondary loop, and is controlled by the primary loop (phase) and the secondary loop (frequency). When FLFC = 1, the secondary loop can be turned off. High frequency components such as 3T and 4T may contain deviations. In such cases, turning the secondary loop off yields better playability. However, in this case the capture range becomes 50kHz. * A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition to the conventional secondary loop. - 112 - CXD3048R Block Diagram 4-1 CLV-W CAV-W Spindle rotation information Clock input 1/2 XTAI XTSL 1/32 Selector VPCO Phase comparator CLV-N 1/2 1/l 1/n CLV-W /CLV-N CAV-W l = 1, 2, 3, 4 (VPCTL0, 1) Microcomputer control 1/K (KSL1, KSL0) n = 1 to 256 (VP7 to 0) VCOSEL2 LPF VCTL VCO2 2/1 MUX VPON 1/M Phase comparator PCO 1/N FILI FILO 1/K (KSL3, KSL2) VCO1 CLTV Digital PLL RFPLL VCOSEL1 - 113 - CXD3048R 4-2. Frame Sync Protection * In normal-speed playback, a frame sync is recorded approximately every 136s (7.35kHz). This signal is used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability. * In the CXD3048R, window protection and forward protection/backward protection have been adopted for frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths; one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is set to 12, and the backward protection counter to 3. Concretely, when the frame sync is being played back normally and then cannot be detected due to scratches, etc., a maximum of 12 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately. Default values. These values can be set as desired by $C commands SFP3 to SFP0 and SRP3 to SRP0. 4-3. Error Correction * In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed-Solomon codes with a minimum distance of 5. * The CXD3048R uses refined super strategy to achieve double correction for C1 and quadruple correction for C2. * In addition, to prevent C2 miscorrection, a C1 pointer is attached to data after C1 correction according to the C1 error status, the playback status of the EFM signal and the operating status of the player. * The correction status can be monitored externally. See Table 4-2. * When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an average value interpolation was made for the data. MNT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MNT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MNT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MNT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C2 correction impossible; C2 correction impossible; Table 4-2. - 114 - No C1 errors; One C1 error corrected; Two C1 errors corrected; C1 correction impossible; No C2 errors; One C2 error corrected; Two C2 errors corrected; Three C2 errors corrected; Four C2 errors corrected; No C1 errors; One C1 error corrected; Description C1 pointer reset C1 pointer reset -- -- C1 pointer set C1 pointer set C1 pointer set C1 pointer set C2 pointer reset C2 pointer reset C2 pointer reset C2 pointer reset C2 pointer reset -- C1 pointer copy C2 pointer set CXD3048R Timing Chart 4-3 Normal-speed PB 400 to 500ns RFCK t = Dependent on error condition MNT3 C1 correction C2 correction MNT2 MNT1 MNT0 Strobe Strobe 4-4. DA Interface * The DA interface supports the 48-bit slot interface. 48-bit slot interface This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. The output format from the bass boost block supports 18 bits and 20 bits in addition to 16 bits. - 115 - Timing Chart 4-4 48-bit Slot Normal-speed Playback LRCK (44.1K) 1 BCK (2.12M) WDCK 2 3 4 5 6 7 8 9 10 11 12 24 PCMD R0 Lch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB - 116 - 48-bit Slot Double-speed Playback LRCK (88.2K) 12 BCK (4.23M) 24 WDCK PCMD R0 Lch MSB (15) L0 Rch MSB CXD3048R Timing Chart 4-5 (DAC output selected) SDSL1 = 1, OBIT1 = 0, OBIT0 = 1 LRCK (44.1K) 1 BCK (2.12M) 2 3 4 5 6 7 8 9 10 11 12 24 - 117 - WDCK PCMD R0 Lch MSB (17) L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB SDSL = 1, OBIT1 = 0, OBIT0 = 0 PCMD R0 Lch MSB (19) L18 L17 L16 L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB CXD3048R CXD3048R 4-5. Digital Out There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD3048R supports type 2 form 1. This LSI supports two kinds of Digital Out generation methods; generation from the PCM data read out from the disc, and generation from the DA interface inputs (PCMDI, LRCKI, BCKI). The timing accuracy of output data depends on the signal accuracy input to XTAI, XTAO pins in CLV-N mode, and the built-in VCO accuracy in VCO-C mode. 4-5-1. Digital Out from PCM Data The Digital Out is generated from the PCM data which is read out from the disc. The clock accuracy of the channel status is automatically set to level II when the crystal clock is used and to level III in CAV-W mode, VCO-C mode or variable pitch mode. In addition, the subcode-Q data matched twice in succession with CRC check are input to the initial 4 bits (bits 0 to 3). DOUT is output when the crystal is 34MHz and XTSL is high in CLV-N or CLV-W mode with DSPB = 1. Therefore, DOUT is set to off by setting the $B command MD2 to "0". Digital Out C bit 0 0 ID0 16 0 1 2 3 4 0 5 0 6 0 7 0 8 1 9 0 10 0 11 0 12 0 13 0 14 0 15 0 From sub Q ID1 COPY Emph 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 32 48 0 176 bit0 to 3 bit29 Subcode-Q control bits that matched twice in succesion with CRCOK VPON or VARION: 1 Crystal: 0 Table 4-5-1. - 118 - CXD3048R 4-5-2. Digital Out from DA Interface Input The Digital Out is generated from the DA interface input. Validity Flag and User Data The Validity Flag is fixed to "0". The User Data is fixed to "0" or it can be output according to the format by setting 0 data. For the Q data, first set the Q1 to Q80 data using the $A90 to $A99 commands, then the set data can be output according to the digital interface format using the $A9A command. In addition, CRC operations are performed internally on the Q81 to Q96 data and then this data is output. The data is output in the order shown in Table 4-5-2. The setting flow is shown in Figs. 4-5 (a) and 4-5 (b). Fig. 4-5 (a) shows the case when changing all the data, and Fig. 4-5 (b) the case when changing the INDEX, movement time and absolute time. 0 0 12 24 36 48 : 1164 0 0 1 1 1 : 1 1 0 0 Q1 Q2 Q3 : Q96 2 0 0 0 0 0 : 0 3 0 0 0 0 0 : 0 4 0 0 0 0 0 : 0 5 0 0 0 0 0 : 0 6 0 0 0 0 0 : 0 7 0 0 0 0 0 : 0 8 0 0 0 0 0 : 0 9 0 0 0 0 0 : 0 10 0 0 0 0 0 : 0 11 0 0 0 0 0 : 0 Table 4-5-2. - 119 - CXD3048R Channel Status Data For the Channel Status Data, bits 0, 6 and 7 are fixed to "0". The following items can be set by bits 1, 2, 3 and 8. a) Digital data/audio data b) Digital copy enabled/prohibited c) With/without emphasis d) Category code (2 types possible) Digital Out C bit 0 0 0 1 2 3 4 0 5 0 6 0 7 0 8 CAT b8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 A/D COPY EMPH SEL En D 0 0 0 16 0 0 0 0 0 0 0 0 0 0 0 0 32 48 0 176 Table 4-5-3. Note) In this method, DOUT can be set to off by setting $B command MD2 to "0" and $34A command DOUT EN to "0". - 120 - CXD3048R START $A900 : $A990 Wait time 13.3ms $A9A0F0 (DON = H, DUP1 = H, DUP0 = H) Set the subcode-Q information. Input with BCD code. Output the subcode-Q information. Start the movement time and absolute time counts. $A9A040 (DON = L, DUP1 = L, DUP0 = L) $A900 : $A990 Wait time 13.3ms Input $A9A0F0 (DON = H, DUP1 = H, DUP0 = H) Stop subcode-Q information output to D-out. Stop the movement time and absolute time counts. Set the subcode-Q information. Input with BCD code. (Output the changed subcode-Q information.) Fig. 4-5(a). Flow Chart for Settings Using Q Data START $A900 : $A990 Wait time 13.3ms $A9A0F0 (DON = H, DUP1 = H, DUP0 = H) Set the subcode-Q information. Input with BCD code. Output the subcode-Q information. Start the movement time and absolute time counts. $A9A0C8 (DUP1 = L, DUP0 = L, DLD = H) $A920 $A930 : $A950 $A970 : $A990 (Stop the movement time and absolute time counts.) INDEX Movement time Absolute time Wait time 13.3ms Note) The INDEX, movement and absolute time data output to D-out while making the settings is all "0". Input $A9A0F0 (DUP1 = H, DUP0 = H, DLD = L) (Output the changed subcode-Q information.) Fig. 4-5(b). Flow Chart for Settings Using Q Data - 121 - CXD3048R Digital Audio Data Input The input signal of the digital audio data is input through the DAC input signal pins PCMDI, LRCKI and BCKI. The input format supports the 48-bit slot, MSB first. Mute Function By setting the command bit DOUT_DMUT to "1", all the audio data portions in the Digital Out output can be set to "0" without altering the Channel Status Data. Input/Output Synchronization Circuit In normal operation, the DAC automatically synchronizes with the input LRCK. However, synchronization may not be achieved when the input data contains much jitter or during power-on, etc. In such cases, internal operation should be forcibly resynchronized by setting the $34A command DOUT WOD to "1". Forced synchronization is also required when the operating frequency is changed such as switching between CLV and CAV, etc. Be sure to set DOUT WOD to "0" and then to "1" for forced resynchronization. Resynchronization clears the internal frame counter so that the count starts over from frame 0 after the resynchronization processing. In cases where automatic resynchronization processing is not desirable or the user wants to do it manually, set the $34A command WINEN to "0" to disable the resynchronization circuit. DOUT Circuit Clock System For the DOUT block, the master clock is set using the clock control command MCSL ($A) employed by the DAC block. Set MCSL to "1" for 768fs, and to "0" for 384fs. - 122 - DOUT Block Input Timing Chart 48-bit slot LRCK 1 BCKI 2 3 4 5 6 7 8 9 10 11 12 24 PCMDI R0 Lch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB - 123 - CXD3048R CXD3048R 4-6. Servo Auto Sequence This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jump, fine search and M-track move are executed automatically. The servo block operates according to the built-in program during the auto sequence execution (when XBUSY = low), so that commands from the CPU, that is $0, 1, 2 and 3 commands, are not accepted. ($4 to E commands are accepted.) When the auto sequencer is used, $9X command A.SEC ON-OFF is turned on. In addition, when using the auto sequence, turn the A.SEQ ON-OFF of register 9 on. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100s after that point. This is to prevent the transfer of erroneous data to the servo when XBUSY changes from low to high by the monostable multivibrator, which is reset by CLOK being low (when XBUSY is low). In addition, a MAX timer is built into this LSI as a countermeasure against abnormal operation due to external disturbances, etc. When the auto sequence command is sent from the CPU, this command assumes a $4XY format, in which X specifies the command and Y sets the MAX timer value and timer range. If the executed auto sequence command does not terminate within the set timer value, the auto sequence is interrupted (like $40). See "[1] $4X commands" concerning the timer value and range. Also, the MAX timer is invalidated by inputting $4X0. Although this command is explained in the format of $4X in the following command descriptions, the timer value and timer range are actually sent together from the CPU. (a) Auto focus ($47) Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-6. The auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search-down). In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E. (b) Track jump 1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on ($17) should be sent beforehand because they are not involved in this sequence. * 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 4-7. Set blind A and brake B with register 5. * 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance with Fig. 4-8. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on. - 124 - CXD3048R * 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 4-9. The track jump count N is set with register 7. Although N can be set to 216 tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps when N is less than 16, and MIRR is used when N is 16 or more. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6. * Fine search When $44 ($45 for REV) is received from the CPU, a FWD (REV) fine search (N-track jump) is performed in accordance with Fig. 4-10. The differences from a 2N-track jump are that a higher precision is achieved by controlling the traverse speed, and a longer distance jump can be performed by controlling the sled. The track jump count N is set with register 7. N can be set to 216 tracks. After kicking the actuator and sled, the traverse speed is controlled based on the overflow G. Set kick D and F with register 6 and overflow G with register 5. Also, sled speed control during traverse can be turned off by causing COMP to fall. Set the number of tracks during which COMP falls with register B. After N tracks have been counted through COUT, the brake is applied to the actuator and sled. (This is performed by turning on the tracking servo for the actuator, and by kicking the sled in the opposite direction during the time for kick D set with register 6.) Then, the tracking and sled servos are turned on. Set overflow G to the speed required to slow up just before the track jump terminates. (The speed should be such that it will come on-track when the tracking servo turns on at the termination of the track jump.) For example, set the target track count N - for the traverse monitor counter which is set with register B, and COMP will be monitored. When the falling edge of this COMP is detected, overflow G can be set again. * M-track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) M-track move is performed in accordance with Fig. 4-11. M can be set to 216 tracks. Like the 2N-track jump, COUT is used for counting the number of moves when M is less than 16, and MIRR is used when M is 16 or more. The M-track move is executed by moving only the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks. In addition, the track and sled servos are turned off after M tracks have been counted through COUT or MIRR unlike for the other jumps. Transfer $25 from the microcomputer after the actuator has stabilized. - 125 - CXD3048R Auto focus Focus search-up FOK = H YES NO FZC = H NO YES Check whether FZC is continuously high for the period of time E set with register 5. FZC = L NO YES Focus servo ON END Fig. 4-6-(a). Auto Focus Flow Chart $47 Latch XLAT FOK FZC BUSY Command for DSSP block $03 Blind E $08 Fig. 4-6-(b). Auto Focus Timing Chart - 126 - CXD3048R 1 Track Track FWD kick sled servo OFF WAIT (Blind A) (REV kick for REV jump) COUT = NO YES Track REV kick WAIT (Brake B) Track, sled servo ON (FWD kick for REV jump) END Fig. 4-7-(a). 1-Track Jump Flow Chart $48 (REV = $49) Latch XLAT COUT BUSY Blind A Command for DSSP block $28 ($2C) $2C ($28) Brake B $25 Fig. 4-7-(b). 1-Track Jump Timing Chart - 127 - CXD3048R 10 Track Track, sled FWD kick WAIT (Blind A) (Counts COUT x 5) COUT = 5 ? NO YES Track, REV kick Checks whether the COUT cycle is linger than overflow C. C = Overflow ? NO YES Track, sled servo ON END Fig. 4-8-(a). 10-Track Jump Flow Chart $4A (REV = $4B) Latch XLAT COUT BUSY Blind A Command for DSSP block COUT 5 counts Overflow C $2A ($2F) $2E ($2B) $25 Fig. 4-8-(b). 10-Track Jump Timing Chart - 128 - CXD3048R 2N Track Track, sled FWD kick WAIT (Blind A) COUT (MIRR) = N Counts COUT for the first 16 times and MIRR for more times. NO YES Track REV kick C = Overflow NO YES Track servo ON WAIT (Kick D) Sled servo ON END Fig. 4-9-(a). 2N-Track Jump Flow Chart $4C (REV = $4D) Latch XLAT COUT (MIRR) BUSY Blind A Command for DSSP block $2A ($2F) COUT (MIRR) N counts $2E ($2B) Overflow C $26 ($27) Kick D $25 Fig. 4-9-(b). 2N-Track Jump Timing Chart - 129 - CXD3048R Fine Search Track Servo ON Sled FWD Kick WAIT (Kick D) Track Sled FWD Kick WAIT (Kick F) Traverse Speed Ctrl (Overflow G) COUT = N? YES NO Track Servo ON Sled REV Kick WAIT (Kick D) Track Sled Servo ON END Fig. 4-10-(a). Fine Search Flow Chart $44 (REV = $45) Latch XLAT COUT BUSY Command for DSSP block Kick D $26 ($27) Kick F $2A ($2F) Traverse Speed Control (Overflow G) & COUT N counts Kick D $27 ($26) $25 Fig. 4-10-(b). Fine Search Timing Chart - 130 - CXD3048R M Track Move Track Servo OFF Sled FWD Kick WAIT (Blind A) Counts COUT for M < 16. Counts MIRR for M 16. COUT (MIRR) = M NO YES Track, Sled Servo OFF END Fig. 4-11-(a). M-Track Move Flow Chart $4E (REV = $4F) Latch XLAT COUT (MIRR) BUSY Blind A Command for DSSP block $22 ($23) COUT (MIRR) M counts $20 Fig. 4-11-(b). M-Track Move Timing Chart - 131 - CXD3048R 4-7. Digital CLV Fig. 4-12 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable. Digital CLV CLVS U/D MDS Error MDP Error Measure Measure CLV P/S 2/1 MUX Oversampling Filter-1 Gain MDS 1/2 Mux Gain MDP + Gain DCLV Oversampling Filter-2 CLV P/S Noise Shape KICK, BRAKE, STOP Modulation PWMI LPWR Mode Select MDP CLVS U/D: MDS error: MDP error: PWMI: Up/down signal from CLVS servo Frequency error for CLVP servo Phase error for CLVP servo Spindle drive signal from the microcomputer for CAV servo Fig. 4-12. Block Diagram - 132 - CXD3048R 4-8. CD-DSP Block Playback Speed In the CXD3048R, the following playback modes can be selected through different combinations of the XTAI, XTSL pins, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency division commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode. Mode 1 2 3 4 5 6 7 XTAI 768Fs 768Fs 768Fs 768Fs 384Fs 384Fs 384Fs XTSL 1 1 0 0 0 0 1 DSPB 0 1 0 1 0 1 1 VCOSEL11 0/1 0/1 1 1 0/1 0/1 0/1 ASHS 0 0 1 1 0 0 0 Playback speed 1x 2x 2x 4x 1x 2x 1x Error correction2 C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: quadruple C1: double; C2: double C1: double; C2: double 1 Actually, the optimal value should be used together with KSL3 and KSL2. 2 When $8 command ERC4 = 1, C2 is quadruple correction even when DSPB = 1. The playback speed can be varied by setting VP0 to VP7 in CAV-W mode. See "[3] Description of Modes" for details. 4-9. Description of DAC Block and Shock-proof Memory Controller Block Circuits The CXD3048R inputs data from the CD-DSP block to the DAC block via the shock-proof memory controller block. The data from the shock-proof memory controller block is output externally as bass-boosted data via the DBB circuit. When not using the DAC block, the data from the shock-proof memory controller block can be output directly to the outside of the LSI. Also, when not using the shock-proof memory controller, the data can be input directly from the CD-DSP block to the DAC block. The DAC block output format supports 16, 18 or 20 bits. - 133 - 4-10. DAC Block Input Timing Fig. 4-13 shows the input timing chart to the DAC block. The CXD3048R can transfer data from the CD-DSP block to the DAC block via an external route. This allows the data to be sent to the DAC block via an audio DSP, etc. Normal-speed Playback LRCKI (44.1k) BCKI (2.12M) 1 2 3 4 5 6 7 8 9 10 11 12 24 PCMDI R0 Lch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 Rch MSB - 134 - Double-speed Playback LRCKI (88.2k) 1 BCKI (4.23M) 2 24 PCMDI R0 Lch MSB (15) L0 Rch MSB CXD3048R Fig. 4-13. Input Timing to the DAC Block CXD3048R 4-11. Description of DAC Block Functions Zero Data Detection When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0" or all "1" has continued for about 300ms (16384/44.1kHz), zero data is detected. Zero data detection is performed independently for the left and right channels. Mute flag output The LRMU pin goes active when any one of the following conditions is met. (when $AA command ORMU = 0) The polarity can be selected by the $A5X command ZDPL. * When zero data is detected * When a high signal is input to the SYSM pin and the state continues for approximately 300ms * When the $A5 command SMUT is set and the state continues for approximately 300ms Attenuation Operation Assuming the attenuation commands X1, X2 and X3, the corresponding audio outputs are Y1, Y2 and Y3 (Y1 > Y3 > Y2). First, the command X1 is sent and then the audio output approaches Y1. When the command X2 is sent before the audio output reaches Y1 (A in the figure), the audio output passes Y1 and approaches Y2. And, when the command X3 is sent before the audio output reaches Y2 (B or C in the figure), the audio output approaches Y3 from the value (B or C in the figure) at that point. 0dB 400 (H) A Y1 B Y3 C Y2 - 000 (H) 23.2 [ms] DAC Block Mute Operation Soft mute Soft mute results and the input data is attenuated to zero when any one of the following conditions is met. * When attenuation data of 000 (h) is set * When $A5 command SMUT is set to "1" * When a high signal is input to the SYSM pin Soft mute off 0dB Soft mute on Soft mute off -dB 23.2 [ms] 23.2 [ms] - 135 - CXD3048R Zero detection mute Analog mute is applied to the respective channel when $AX command ZMUTA is set to "0" and zero data is detected for the left or right channel. (See "Zero data detection".) When $AX command ZMUTA is set to "0", analog mute is applied even if the mute flag output condition is met. LRCK Synchronization Synchronization is performed at the first rising edge of the LRCK input when reset. After that, synchronization is lost when the LRCK input frequency changes, etc., so resynchronization must be performed. The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed changes such as the following cases. * When the XTSL pin switches between high and low * When the $9 command DSPB setting changes * When the $A4 command MCSL setting changes * When operation switches between CLV mode and CAV mode For resynchronization, set the $A5 command XWOC to "1", wait for one LRCK cycle or more, and then set XWOC to "0". Digital High and Bass Boost High and bass boost without external parts is possible using the built-in digital filter. Perform the following operations when turning boost off or when lowering the current boost level. 1. Set $A5X command BSTCL to "1". 2. Wait 20ms or more, set the boost level or turn boost off, then set $A5X command BSTCL to "0". High-cut Filter This filter lowers the high-frequency level by approximately 8dB. The frequency response is shown in Fig. 4-14. 0.00 -2.00 Gain [dB] -4.00 -6.00 -8.00 10 100 Frequency [Hz] 1k 10k Fig. 4-14. High-Cut Filter Frequency Response - 136 - CXD3048R Compressor, Dynamic High and Bass Boost 1. Frequency Response and I/O Characteristics Fig. 4-15 shows the frequency response for dynamic high boost and bass boost. This figure shows the frequency response for a high boost turnover frequency of 5kHz and a bass boost turnover frequency of 160Hz. The boost level and turnover frequency can be set independently for high boost and bass boost. In addition, all frequencies are lowered by approximately 2dB in order to prevent clipping, so the medium frequencies are -2dB output. The high boost and bass boost levels indicate the relative values from this level. Next, the compressor, high boost and bass boost I/O characteristics are shown in Fig. 4-17. As shown in this figure, the compressor characteristics span all frequencies. In addition, the high boost and bass boost characteristics are for when the input signal is sufficiently higher or lower than the turnover frequency. The boost levels can be set independently. Uth and Lth on the vertical axis are the gain control threshold values, and the desired output value can be taken from the area enclosed by the parallelograms near these levels. The Uth and Lth settings are described hereafter. 20.00 (4) (1) HBSL1 = 0, HBSL0 = 0, BBSL1 = 0, BBSL0 = 0 (2) HBSL1 = 0, HBSL0 = 1, BBSL1 = 0, BBSL0 = 1 (3) HBSL1 = 1, HBSL0 = 0, BBSL1 = 1, BBSL0 = 0 (4) HBSL1 = 1, HBSL0 = 1, BBSL1 = 1, BBSL0 = 1 18.00 16.00 (3) 14.00 12.00 (2) Gain [dB] 10.00 8.00 (1) 6.00 4.00 2.00 0.00 -2.00 10 100 Frequency response [Hz] 1k 10k Fig. 4-15. Digital Bass Boost Frequency Response - 137 - CXD3048R 2. Settings When performing dynamic processing, the auditory volume and other characteristics change according to the boost levels and various other settings. The values that can be set by the serial commands and the resulting effects are described below. 2-1. Boost Level The boost level can be set independently for the compressor, high boost and bass boost. Boost level here refers to the maximum boost level when a low level signal is input. The boost level changes over time when a high level signal is input in order to prevent clipping. 2-2. Gain Control Thresholds The gain control thresholds are Uth and Lth. When the level exceeds Uth, the gain is reduced; when the level falls below Lth, the gain is increased. If both Uth and Lth are set to large values, the volume increases and the respective boost effects are emphasized. On the other hand, some sources may be clipped due to the balance with the boost level. These values can be set independently for the compressor and high/bass boost. The same values are shared for high and bass boost. 2-3. Attack Time, Release Time The attack time represents the speed at which the gain is reduced after high level input, and the release time represents the speed at which the gain is increased when the input level suddenly becomes smaller. If these values are set to "fast", the boost effects increase. Like the gain control thresholds, these values can be set independently for the compressor and high/bass boost. 2-4. Envelope Detection Release Time This sets the output signal envelope coefficient used for gain control. When set to "fast", the boost effects increase. This setting is shared by compressor and high/bass boost. High boost Bass boost +10dB +14dB +18dB +22dB Attack time Standard Slow Slow Slow Release time Standard Standard Standard Standard Lch -12dB -12dB -12dB -12dB Uch -1.9dB -1.9dB -1.9dB -1.9dB Table 4-16. Recommended Dynamic Bass and High Boost Settings - 138 - CXD3048R Input [dB] 0 Uth Lth Fig. 4-17. Dynamic Processing I/O Characteristics Uth [dB] Compressor High boost Bass boost -8.0 -1.9/-0.9 -1.9/-0.9 Lth [dB] -23 -12/-4.4 -12/-4.4 Boost level [dB] 6 4/6/8/10 10/14/18/22 - 139 - Output [dB] CXD3048R 4-12. LPF Block The CXD3048R contains a secondary active LPF. The LPF block application circuit is shown in Fig. 4-18. AOUT1 (2) 100 Analog out 2200pF VREFL (R) 1F Fig. 4-18. LPF External Circuit - 140 - CXD3048R 4-13. Description of Shock-proof Memory Controller Block Functions 4-13-1. DRAM I/F A 4M DRAM or 16M DRAM can be selected as the external buffer RAM. The 16M DRAM supports either row address 212 and column address 210 or row address 211 and column address 211. Refresh is performed by data access, and the refresh cycle is approximately 11.6ms when 4M DRAM is selected, or approximately 46.4ms (210 x 212) or 23.2ms (211 x 211) when 16M DRAM is selected. In addition, XRAS-only-refresh is executed 14 times in order to initialize the RAM after the power is turned on and the DRAM, which is to be used by the $A4X commands RSL1 and RSL0, is selected. Data access to the DRAM is not possible during this period. XRST XRAS Approximately 5.67s 14 times 4-13-2. Switching from Data Through Mode to Shock-proof The CXD3048R performs refresh by data access. When switching from (1) Shock-proof mode to (2) data through mode to (3) Shock-proof mode, be sure to reset all of WA, VWA and RA before performing data access for (3). - 141 - CXD3048R 4-13-3. CPU Serial Data Output (when $A7X STASEL = 1) Data is read out by setting the XSOEO command low and inputting SQCK. The data contents at the falling edge of the XSOEO command are output from the SQSO pin at the falling edge of SCK. XSOEO SQCK Invalid SQSO D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0: XWPHD D1: QRCVD D2: XEMP D3: AM15 D4: AM16 D5: AM17 D6: AM18 D7: AM19 D8: AM20 D9: AM21 D10: XFUL D11: ROF Data write to DRAM prohibited signal (low for XFUL + ROF + WRNG) Indicates whether XQOK was registered as a defined address after it was sent. (High = registration OK) Low when the DRAM is empty of valid data. (VWA = RA) Address monitor; indicates the amount of valid data remaining. Address monitor; indicates the amount of valid data remaining. Address monitor; indicates the amount of valid data remaining. Address monitor; indicates the amount of valid data remaining. Address monitor; indicates the amount of valid data remaining. Address monitor; indicates the amount of valid data remaining. Address monitor; indicates the amount of valid data remaining. Low when the DRAM is full and there is no write area. High when the DSP RAM has overflowed. Note) When GRSCOR is low, QRCVD is high when data write to the DRAM is enabled, even if a negative pulse is input to XQOK. - 142 - CXD3048R 4-13-4. Data Linking In order to restart write after PCM data write to the DRAM has been interrupted due to sound skipping or other factors, continuity must be maintained between the data written last and the subsequent data to be written. Conventional systems fix an aim at the data linking point, compare the preceding DRAM reference data with the data read from the disc, and then link the data when matching data is detected. However, when using music software where a fixed pattern is repeated, this system may link the data at an incorrect point. In addition, if pre-value hold or interpolation is performed at the point to be linked, data linking may not be possible at all. In order to eliminate these data linking errors, the CXD3048R generates a crystal accuracy SCOR (= GRSCOR) synchronized to the PCM data to allow data linking along the time axis, thus greatly increasing the data linking accuracy. 4-13-5. Data Processing The CXD3048R accumulates PCM data from the CD-DSP block in an external buffer and then inputs the data to the DAC block in sync with the internally generated Fs system clock. At this time, the PCM data is loaded and read out at the same rate during normal playback, so data does not accumulate in the buffer RAM. Therefore, the loading rate must be increased. This is accomplished by setting the CD-DSP block to doublespeed mode and doubling the loading rate until the RAM is full. When the RAM becomes full, data regeneration from the disc stops temporarily and the RAM data is read out to create an empty area, at which point loading is restarted. These operations are then repeated to effectively use the entire area inside the RAM. CD-DSP Shock-proof DAC 4M DRAM PCM Data Flow (Example for 4M x 1 mode) 4-13-6. System Outline (when SLXQOK = 1 and SLXWRE = 1) The addresses for accessing the buffer RAM data consist of a readout address (RA) and a write address (WA). The data to be written is not always correct, and the subcodes, etc. must be constantly checked to make sure the data is correct and there is no sound skipping. The CXD3048R checks subcode-Q using the CPU, and defines the data by inputting a negative pulse to the XQOK pin. This defined address (VWA) is loaded to the internal register and the data between VWA and RA is treated as valid data. WA advances at a speed twice that of RA, and RA is written by WA and read out sequentially in the order registered by VWA. When RA catches up to VWA, there is no more valid data and readout is prohibited (XEMP = low). In addition, when WA catches up to RA, the buffer is full and write is prohibited (XWIH = low). In this manner, write to the RAM is interrupted when the RAM becomes full and there is no write area or when sound skipping caused by scratches, external disturbances or other factors is detected. Data WA continuity must be ensured in order to restart write. Therefore, the VWA CXD3048R returns to the last defined address, and the CPU accesses the defined address point it sent last (actually the data slightly before that point) and reads the subcode-Q after the rising edge of SCOR. If the RA subcode-Q matches the last defined address, XWRE is made to fall and write is restarted when GRSCOR comes high within 7ms. Note 1) If XWRE is made to fall when GRSCOR is low, XWIH goes low and the write prohibited state results. Valid data Note 2) When GRSCOR is low, VWA is not updated even if a negative pulse is input to XQOK. Therefore, set XQOK high while GRSCOR is low. - 143 - CXD3048R 4-13-7. Data Write (when SLXQOK = 1 and SLXWRE = 1) The PCM data input from the DSP is loaded according to the Fs system clock inputs (BCKI, WDCI and LRCI), and is written sequentially to the external DRAM according to WA when the XWRE pin input goes low and internal write is enabled (XWIH pin output = high). The written data must be checked by some means or other. The CXD3048R assumes data checking with subcode-Q. In this case, the CPU reads subcode-Q triggered by the SCOR signal output from the DSP to determine whether sound skipping occurred. If sound skipping is not detected, the CPU inputs a negative pulse to the XQOK pin during the GRSCOR high interval which comes within 7ms, and the data written to WA thus far is registered to VWA as data without sound skipping. SCOR No sound skipping = CRC OK SUBQ No sound skipping = CRC NG GRSCOR XQOK WA VWA Write prohibition is determined by the internal status or by an external command. When prohibited by the internal status, the XWIH pin goes low, and this status is established when any one of the following conditions is met. 1. There is no empty area in the DRAM. XFUL = low 2. The DSP RAM has overflowed. ROF = high 3. XWRE was made to fall when GRSCOR is low. WRNG = high 4. The DRAM write speed exceeds the set value. SPOVER = high (when $A7 command XWIH1 = 1) 5. Access to DRAM in the shock-proof memory controller block failed. NOWR = high (when $A7 command XWIH2 = 1) 6. The number of C2PO errors exceeds the set value. monC2PO = high ($AE command WTC C2PO = 1) 7. Write is prohibited by the external input (A11 pin). (when $A7 command A11 SEL = 1 and $AE command WTC C2PO = 1) When the XWIH pin goes low due to the above conditions, the CPU must set the XWRE pin high and then the XWIH pin high. After the CPU sends XQOK, it must check whether XQOK was registered as a defined address. This is because if the above conditions arise at the same time XQOK is sent, XQOK becomes invalid and the addresses defined by the CPU and the CXD3048R may not match. Therefore, the XWIH pin output is used as the XQOK recognition signal (QRCVD) while XQOK is low. When QRCVD is high, this indicates that XQOK was correctly registered as a defined address (VWA was updated). When QRCVD is low, this indicates one of the following conditions. 1. Write is prohibited due to the above conditions. 2. XWRE is high. Regarding condition 2, if XQOK is sent while the XWRE pin is high, WA, VWA and RA are all reset (when GRSCOR is high). - 144 - CXD3048R 4-13-8. Data Readout (when SLXQOK = 1 and SLXWRE = 1) When data write starts, there is no valid data in the RAM so the XEMP pin is low. The XWRE pin goes from high to low, and if there is no sound skipping or other problems with the CRC check at the next SCOR, XQOK is sent during the GRSCOR high interval which comes within 7ms, and the defined address and valid data are registered. At this point, the XEMP pin goes high for the first time and readout is enabled. Data readout follows RA, and is performed in sync with the internally generated Fs system clocks. The readout data and the Fs system clocks are output from the DATA and the BCK and LRCK pins, respectively. RA is the address for reading out the written data that has been validated by VWA, and the area from VWA to RA is the amount of valid data (|VWA - RA|). The upper 5 bits are output as AM21 to AM17. When RA catches up to VWA and there is no more valid data (|VWA - RA| = 0), the XEMP pin goes low and readout is prohibited. When this state occurs, the CPU must set the XRDE pin high to prohibit readout. To restart readout, valid data must be registered as described above. The XEMP pin is held low until valid data is registered. XWRE XQOK XEMP XRDE Note) After the XWRE pin goes from high to low, readout is enabled when valid data is registered by the first XQOK. However, ensuring some difference between VWA and RA is recommended in consideration of CRC NG, etc. See also "Application Notes" for the control of the shock-proof memory controller block. - 145 - CXD3048R 4-14. CPU to DRAM Access Function The CXD3048R can establish a special area in the DRAM. This allows a microcomputer to read and write optional 16-bit data to a portion of the DRAM area. This function can be used to store and optionally read out demodulated CD TEXT data, etc. The range of this special area is set by $A7, and can be selected in 8 steps from 32K to 2M bits. Table 4-19 shows the addresses which can be specified according to the used DRAM capacity and the special area setting value. In addition, the address specification method can be selected from absolute and relative specification. RSL 10 MSL 210 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DRDR19 to DRDR0 specification range -------------- 00000 to 007FF 00000 to 00FFF 00000 to 01FFF 00000 to 03FFF 00000 to 07FFF 00000 to 0FFFF 00000 to 1FFFF -------------- 00000 to 007FF 00000 to 00FFF 00000 to 01FFF 00000 to 03FFF 00000 to 07FFF 00000 to 0FFFF 00000 to 1FFFF 4M setting 00 16M setting 11 Table 4-19. - 146 - CXD3048R Write and Read by Absolute Address Specification WRITE READ Set $A8 commands XSOEO2 to "1" and SDTO OUT to "1" Set $A8 commands XSOEO2 to "1" and SDTO OUT to "1" Transfer an optical address with the $A9F command L (Req NG) (A) Check SQSO H (Req OK) Write optional data with the $A9E command (DRWR = 1, DRADR = 1) (B) Set $A8 commands XSOEO2 to "1" and SDTO OUT to "0" Transfer an optional address with the $A9F command L (Req NG) Check SQSO (1) H (Req OK) Generate a readout request with $A9E command (DRWR = 0, DRADR = 1) Change $A8 command XSOEO2 from "1" to "0" END Check SQSO L (NG) (2) H (Data Ready) Read 16-bit data from SQSO and SQCK Set $A8 commands XSOEO2 to "1" and SDTO OUT to "0" END - 147 - CXD3048R Write Communication Timing Command $A8 $A9F $A9E $A8 XSOEO2 STDO OUT SQSO Readout Communication Timing Command $A8 $A9F $A9E $A8 $A8 XSOEO2 STDO OUT SQCK SQSO (1) (2) D0 D15 Readout Communication Operation (1) Set STDO OUT to "1" to switch the serial communication line for special memory. (2) Send the address command ($A9F), then check whether the DRAM related processing has completed using the SQSO pin. (3) The data read out from the DRAM is loaded to the communication block inside the LSI by sending the read command ($A9E) and causing XSOEO2 to fall ($A8). However, the DRAM related processing requires a check as to whether the data was loaded properly using the SQSO pin. (4) The readout data is output from the SQSO pin by inputting 16 clocks from the SQCK pin. - 148 - CXD3048R Write and Read by Relative Address Specification WRITE READ Set $A8 commands XSOEO2 to "1" and SDTO OUT to "1" Write the absolute address (A) on page 147 NEXT PENDING NEXT Set $A8 commands XSOEO2 to "1" and SDTO OUT to "1" Write the absolute address (B) on page 147 PENDING Write optional data with the $A9E command (DRWR = 1, DRADR = 0) Generate a readout request with $A9E command (DRWR = 0, DRADR = 0) L (Req NG) Check SQSO H (Req OK) N Check SQSO H (Req OK) L (Req NG) END Y Set $A8 commands XSOEO2 to "1" and SDTO OUT to "0" Change $A8 command XSOEO2 from "1" to "0" and set SDTO OUT to "1" L (NG) Check SQSO H (Data Ready) END Read 16-bit data from SQSO and SQCK N END Y Set $A8 commands XSOEO2 to "1" and SDTO OUT to "0" END - 149 - CXD3048R 4-15. Asymmetry Correction Fig. 4-20 shows the block diagram and circuit example. ASYE command ASYO R1 RFAC + - R1 R2 + - R1 ASYI R1 BIAS R1 2 = R2 5 Fig. 4-20. Asymmetry Correction Application Circuit - 150 - CXD3048R 4-16. CD TEXT Data Demodulation * In order to demodulate the CD TEXT data, set the command $8 Data 6 D3 TXON to "1". While TXON is "1", the CD TEXT demodulation circuit occupies the EXCK and SBSO pins, so connect EXCK to low and do not use the data output from SBSO. Also, 26.7ms (max.) are required to demodulate the CD TEXT data correctly after TXON is set to "1". * The CD TEXT data is output by switching the SQSO pin with the command. The CD TEXT data output is enabled by setting the command $8 Data 6 D2 TXOUT to "1". To read data, the readout clock should be input to SQCK. * The readable data are the CRC counting results for each pack and the CD TEXT data (16 bytes) except for CRC data. * When the CD TEXT data is read, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first. * Data which can be stored in the LSI is 1 packet (4 packs). TXON CD TEXT Decoder EXCK SBSO Subcode Decoder SQCK SQSO TXOUT Fig. 4-21. Block Diagram of CD TEXT Demodulation Circuit - 151 - SCOR Subcode Q Data SQSO CRCF 80 Clocks SQCK 4 bits CRC 4 bits 0 16 Bytes Pack1 16 Bytes Pack2 520 Clocks 16 Bytes Pack3 16 Bytes Pack4 CRCF TXOUT (command) - 152 - CRC Data LSB SQSO CRC CRC CRC CRC ID1 (Pack1) MSB LSB R2 W1 V1 U1 T1 S1 R1 U3 T3 S3 ID2 (Pack1) MSB LSB R3 W2 V2 U2 ID3 (Pack1) 4 3 2 1 0 0 0 0 S2 T2 W4 V4 U4 T4 S4 SQCK TXOUT (command) Fig. 4-22. CD TEXT Data Timing Chart CXD3048R CXD3048R [5] Description of Servo Signal Processing System Functions and Commands 5-1. General Description of Servo Signal Processing System (VDD: Supply voltage) Focus servo Sampling rate: Input range: Output format: Other: 88.2kHz (when MCK = 128Fs) 1/4VDD to 3/4VDD 7-bit PWM Offset cancel Focus bias adjustment Focus search Gain-down Defect countermeasure Auto gain control Tracking servo Sampling rate: Input range: Output format: Other: 88.2kHz (when MCK = 128Fs) 1/4VDD to 3/4VDD 7-bit PWM Offset cancel E:F balance adjustment Track jump Gain-up Defect countermeasure Drive cancel Auto gain control Vibration countermeasure Sled servo Sampling rate: Input range: Output format: Other: 345Hz (when MCK = 128Fs) 1/4VDD to 3/4VDD 7-bit PWM Sled move FOK, MIRR, DFCT signal generation RF signal sampling rate: 1.4MHz (when MCK = 128Fs) Input range: 1/4VDD to 3/4VDD Other: RF zero level automatic measurement - 153 - CXD3048R 5-2. Digital Servo Block Master Clock (MCK) The clock with 2/3 frequency of the crystal is supplied to the digital servo block. XT4D and XT2D are $3F commands, and XT1D is a $3E command. (Default is "0" for each command) The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical. Mode 1 2 3 4 5 6 7 XTAI 384Fs 384Fs 384Fs 768Fs 768Fs 768Fs 768Fs FSTO 256Fs 256Fs 256Fs 512Fs 512Fs 512Fs 512Fs XTSL -- -- 0 -- -- -- 1 XT4D -- -- 0 -- -- 1 0 XT2D -- 1 0 -- 1 0 0 Table 5-1. XT1D 1 0 0 1 0 0 0 Frequency division ratio 1 1/2 1/2 1 1/2 1/4 1/4 MCK 256Fs 128Fs 128Fs 512Fs 256Fs 128Fs 128Fs Fs = 44.1kHz, --: don't care - 154 - CXD3048R 5-3. DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 5-3.) The CXD3048R can measure the averages of RFDC, VC, FE and TE and compensate these signals using the measurement results to control the servo effectively. This AVRG measurement and compensation is necessary to initialize the CXD3048R, and is able to cancel the DC offset. AVRG measurement takes the levels applied to the VC, FE, RFDC and TE pins as the digital average values of 256 samples, and then loads these values into each AVRG register. The AVRG measurement commands are D15 (VCLM), D13 (FLM), D11 (RFLM) and D4 (TCLM) of $38. Measurement is on when the respective command is set to "1". AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is received. The completion of AVRG measurement operation can be monitored by the SENS pin. (See Timing Chart 5-2.) Monitoring requires that the upper 8 bits of the command register are 38 (h). XLAT 2.9 to 5.8ms SENS (= XAVEBSY) Max. 1s AVRG measurement completed Timing Chart 5-2. - 155 - CXD3048R 5-4. E:F Balance Adjustment Function (See Fig. 5-3.) When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS search, the traverse waveform appears in the TE signal due to disc eccentricity. In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold filter by setting D5 (TBLM) of $38 to "1". The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC register value is established when TBLM returns to "0". Next, setting D2 (TLC2) of $38 to "1" compensates the values obtained from the TE and SE input pins with the TRVSC register value (subtraction), allowing the E:F balance offset to be adjusted. (See Fig. 5-3.) 5-5. FCS Bias (Focus Bias) Adjustment Function The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to "1". (See Fig. 5-3.) When D11 = 0 and D10 = 1 is set by $34F, the FBIAS register value can be written using the 9-bit value of D9 to D1 (D9: MSB). In addition, the RF jitter can be monitored by setting the $8 command SOCT to "1". (See "DSP Block Timing Chart".) The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to "1". The FBIAS register functions as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0. The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A. When using the FBIAS register as a counter, the counter stops when the value set beforehand in FBL9 to FBL1 of $34 matches the FCSBIAS value. Also, if the upper 8 bits of the command register are $3A at this time, SENS goes high and the counter stop can be monitored. A FBIAS setting value (FB9 to FB1) B C LIMIT value (FBL9 to FBL1) SENS value A: Register mode B: Counter mode C: Counter mode (when stopped) Here, assume the FBIAS setting value FB9 to FB1 and the FBIAS LIMIT value FBL9 to FBL1 are set in status A. For example, if command registers FBUP = 0, FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from this status, down count starts from status A and approaches the set LIMIT value. When the LIMIT value is reached and the FBIAS value matches FBL9 to FBL1, the counter stops and the SENS pin goes high. Note that the up/down counter counts at each sampling cycle of the focus servo filter. The number of steps by which the count value changes can be selected from 1, 2, 4 or 8 steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to 1/512 x VDD/2. - 156 - CXD3048R RFDC from A/D RF AVRG register - RFLC to RF In register SE from A/D - TLC1 * TLD1 TLC2 * TLD2 - to SLD In register TE from A/D - - to TRK In register TE AVRG register TLC1 TRVSC register TLC2 FE from A/D FE AVRG register - FLC1 FBIAS register + FBON to FCS In register FLC0 - to FZC register Fig. 5-3a. RFDC from A/D RF AVRG register - RFLC to RF In register SE from A/D - TLC0 * TLD0 TLC2 * TLD2 - to SLD In register TE from A/D - TLC0 VC AVRG register TRVSC register TLC2 - to TRK In register VCLC FE from A/D FE AVRG register - FBIAS register + FBON to FCS In register FLC0 - to FZC register Fig. 5-3b. - 157 - CXD3048R 5-6. AGCNTL (Automatic Gain Control) Function The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate servo loop gain. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of the command register are 38 (h), the completion of AGCNTL operation can be confirmed by monitoring the SENS pin. (See Timing Chart 5-4 and "Description of SENS Signals".) Setting D9 and D8 of $38 to "1" sets FCS (focus) and TRK (tracking) respectively to AGCNTL operation. Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described hereafter) must be disabled. XLAT Max. 11.4s SENS (= AGOK) AGCNTL completion Timing Chart 5-4. Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking AGCNTL) due to AGCNTL. These coefficients change from 01 to 7F (h), and they must also be set within this range when written externally. After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from the SENS pin with the serial readout function (described hereafter). AGCNTL related settings The following settings can be changed with $35, $36 and $37. FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (h) TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (h) AGS; Self-stop on/off AGJ; Convergence completion judgment time AGGF; Internally generated sine wave amplitude (AGF) AGGT; Internally generated sine wave amplitude (AGT) AGV1; AGCNTL sensitivity 1 (during rough adjustment) AGV2; AGCNTL sensitivity 2 (during fine adjustment) AGHS; Rough adjustment on/off AGHT; Fine adjustment time Note) Converging servo loop gain values can be changed with the FG6 to FG0 and TG6 to TG0 setting values. In addition, these setting values must be within the effective setting range. The default settings aim for 0dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary. - 158 - CXD3048R AGCNTL default operation has two stages. In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select 256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value. The sensitivity at this time can be selected from two types with AGV1. In the second stage, the AGCNTL coefficient is finely adjusted with relatively low sensitivity to further approach the appropriate value. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the CXD3048R confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode) This self-stop mode can be canceled by setting AGS to "0". In addition, the first stage is omitted for AGCNTL operation when AGHS is set to "0". An example of AGCNTL coefficient transitions during AGCNTL operation with various settings is shown in Fig. 5-5. Initial value Slope AGV1 AGCNTL coefficient value Slope AGV2 Convergence value AGHT AGCNTL Start SENS AGJ AGCNTL completion Fig. 5-5. Note) Fig. 5-5 shows the case where the AGCCNTL coefficient converges from the initial value to a smaller value. - 159 - CXD3048R 5-7. FCS Servo and FCS Search (Focus Search) The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.) Register name Command D23 to D20 D19 to D16 1 0 -- -- FOCUS SERVO ON (FOCUS GAIN NORMAL) 1 1 -- -- FOCUS SERVO ON (FOCUS GAIN DOWN) 0 FOCUS CONTROL 0000 0 --0-- 0 --0-- 0 --0 0 0 --0 0 FOCUS SERVO OFF, 0V OUT FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP --: don't care Table 5-6. FCS Search FCS search is required in the course of turning on the FCS servo. Fig. 5-7 shows the signals for sending commands $00 $02 $03 and performing only FCS search operation. Fig. 5-8 shows the signals for sending $08 (FCS on) after that. $00 $02 $03 $00 $02 $03 $08 FCSDRV 0 FCSDRV RF FOK FZC comparator level FE 0 RF FOK FE 0 FZC FZC Fig. 5-7. Fig. 5-8. - 160 - CXD3048R 5-8. TRK (Tracking) and SLD (Sled) Servo Control The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 5-9.) When the upper 4 bits of the serial data are 2 (h), TZC is output to the SENS pin. Register name Command D23 to D20 D19 to D16 0 0 -- -- TRACKING SERVO OFF 0 1 -- -- TRACKING SERVO ON 1 0 -- -- FORWARD TRACK JUMP 1 1 -- -- REVERSE TRACK JUMP ----0 0 ----0 1 ----1 0 ----1 1 SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE --: don't care Table 5-9. 2 TRACKING MODE 0010 TRK Servo The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36. In addition, when the TRK servo is on and D17 of $1 is set to "1", the TRK servo filter switches to gain-up mode. The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. The CXD3048R has 2 types of gain-up filter structures in TRK gain-up mode which can be selected by setting D16 of $1. (See Table 5-17.) SLD Servo The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by multiplying this value by 1x, 2x, 3x, or 4x set using D17 and D16 when D18 = D19 = 0 is set with $3. (See Table 5-10.) SLD MOV must be performed continuously for 50s or more. In addition, if the LOCK input signal goes low when the SLD servo is on, the SLD servo turns off. Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off. These operations are disabled by setting D6 (LKSW) of $38 to "1". Register name Command D23 to D20 D19 to D16 0 000 SLED KICK LEVEL (basic value x 1) SLED KICK LEVEL (basic value x 2) SLED KICK LEVEL (basic value x 3) SLED KICK LEVEL (basic value x 4) Table 5-10. - 161 - 3 SELECT 0011 0 001 0 010 0 011 CXD3048R 5-9. MIRR and DFCT Signal Generation The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and loaded. The MIRR and DFCT signals are generated from this RF signal. MIRR Signal Generation The loaded RF signal is applied to peak hold and bottom hold circuits. An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is generated from the average of this envelope waveform. The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value from the peak hold value with this MIRR comparator level. (See Fig. 5-11.) The bottom hold speed and mirror sensitivity can be selected from four values using D7 and D6, and D5 and D4, respectively, of $3C. RF Peak Hold Bottom Hold Peak Hold - Bottom Hold MIRR Comp (Mirror comparator level) H MIRR L Fig. 5-11. DFCT Signal Generation The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is generated by comparing the difference between these two peak hold waveforms with the DFCT comparator level. (See Fig. 5-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. RF Peak Hold1 Peak Hold2 Peak Hold2 - Peak Hold1 SDF (Defect comparator level) DFCT H L Fig. 5-12. - 162 - CXD3048R 5-10. DFCT Countermeasure Circuit The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. Specifically, this operation is achieved by detecting scratches and defects with the DFCT signal generation circuit, and when DFCT goes high, applying the low-frequency component of the error signal before DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 5-13.) In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38 to "1". Hold filter Error signal Input register DFCT Hold register EN Servo filter Fig. 5-13. 5-11. Anti-shock Circuit When vibrations occur in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures. Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (See Fig. 5-14.) The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator level is practically variable by adjusting the value of the anti-shock filter output coefficient K35. This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See Table 5-17.) This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up mode by inputting high level to the ATSK pin. When the upper 4 bits of the command register are 1 (h), vibration detection can be monitored from the SENS pin. It can also be monitored from the ATSK pin by setting $3F command ASOT to "1". ATSK TE Anti-shock filter Comparator SENS TRK gain-up filter TRK gain normal filter TRK PWM Gen. Fig. 5-14. - 163 - CXD3048R 5-12. Brake Circuit Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. The brake circuit prevents these phenomenon. In principle, the brake circuit uses the tracking drive as a brake by cutting the unnecessary portions utilizing the 180 offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15 and 5-16.) Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal. The brake circuit can be turned on and off by D18 of $1. (See Table 5-17.) In addition, the low frequency for the tracking drive after masking can be boosted. (SFBK1 and SFBK2 of $34B) Inner track Outer track FWD REV JMP JMP Servo ON TRK DRV Outer track Inner track REV FWD JMP JMP Servo ON TRK DRV RF Trace MIRR TE 0 RF Trace MIRR TE TZC Edge TRKCNCL 0 0 TZC Edge TRKCNCL TRK DRV (SFBK OFF) TRK DRV (SFBK ON) SENS TZC out TRK DRV (SFBK OFF) TRK DRV (SFBK ON) SENS TZC out 0 0 0 Fig. 5-15. Register name Command D23 to D20 D19 to D16 1 0 -- -- ANTI SHOCK ON 0 -- -- -- ANTI SHOCK OFF -- 1 -- -- BRAKE ON 1 TRACKING CONTROL 0001 -- 0 -- -- BRAKE OFF ----0-- ----1-- -- ---- 1 -- ---- 0 Fig. 5-16. TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2 Fig. 5-17. - 164 - --: don't care CXD3048R 5-13. COUT Signal The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by loading the MIRR signal at both edges of the TZC signal. The used TZC signal can be selected from among three different phases according to the COUT signal application. * HPTZC: For 1-track jumps Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a cut-off 1kHz digital HPF; when MCK = 128Fs.) * STZC: For COUT generation when MIRR is externally input and for applications other than COUT generation. This is generated by sampling the TE signal at 700kHz. (when MCK = 128Fs) * DTZC: For high-speed traverse Reliable COUT signal generation with a delayed phase STZC signal. Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance with the MIRR signal delay during high-speed traverse. The COUT signal output method is switched with D15 and D14 of $3C. When D15 = 1: STZC When D15 = 0 and D14 = 0: HPTZC When D15 = 0 and D14 = 1: DTZC When DTZC is selected, the delay can be selected from two values with D14 of $36. 5-14. Serial Readout Circuit The measurement and adjustment results specified beforehand by serial command $39 can be read out from the SENS pin by inputting the readout clock to the SCLK pin. (See Fig. 5-18, Table 5-19 and "Description of SENS Signals".) Specified commands See the table on page 180. XLAT tDLS tSPW SCLK 1/fSCLK Serial Readout Data (SENS pin) *** MSB *** LSB Fig. 5-18. Item SCLK frequency SCLK pulse width Delay time Symbol fSCLK Min. 31.3 15 Typ. Max. 16 Unit MHz ns s tSPW tDLS Table 5-19. During readout, the upper 8 bits of the command register must be 39 (h). - 165 - CXD3048R 5-15. Writing to Coefficient RAM The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and transfer from the ROM to the RAM is completed approximately 40s (when MCK = 128Fs) after the XRST pin rises. (The coefficient RAM cannot be rewritten during this period.) After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient RAM. The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and D7 to D0 as the data. Coefficient rewriting is completed 11.3s (when MCK = 128Fs) after the command is received. When rewriting multiple coefficients continuously, be sure to wait 11.3s (when MCK = 128Fs) before sending the next rewrite command. 5-16. PWM Output FCS, TRK and SLD PWM format outputs are described below. In particular, FCS and TRK use a double oversampling noise shaper. Timing Chart 5-20 and Fig. 5-21 show examples of output waveforms and drive circuits. MCK (5.6448MHz) Output value +A SLD 64tMCK SFDR SRDR AtMCK AtMCK 64tMCK 64tMCK Output value -A Output value 0 FCS/TRK 32tMCK FFDR/ TFDR FRDR/ TRDR A tMCK 2 32tMCK A tMCK 2 A tMCK 2 A tMCK 2 32tMCK 32tMCK 32tMCK 32tMCK tMCK = 1 180ns 5.6448MHz Timing Chart 5-20. VCC R R RDR FDR R R VEE DRV Fig. 5-21. Drive Circuit - 166 - CXD3048R 5-17. Servo Status Changes Produced by LOCK Signal When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW) of $38 to "1" deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low. This enables microcomputer control. 5-18. Description of Commands and Data Sets $34 D15 0 D14 KA6 D13 KA5 D12 KA4 D11 KA3 D10 KA2 D9 KA1 D8 KA0 D7 KD7 D6 KD6 D5 KD5 D4 KD4 D3 KD3 D2 KD2 D1 KD1 D0 KD0 When D15 = 0. KA6 to KA0: Coefficient address KD7 to KD0: Coefficient data $348 (preset: $348 000) D15 1 D14 0 D13 0 D12 0 D11 D10 D9 D8 D7 0 D6 0 D5 0 D4 D3 D2 D1 0 D0 0 PGFS1PGFS0PFOK1PFOK0 MRS MRT1 MRT0 These commands set the GFS signal hold time. The hold time is inversely proportional to the playback speed. PGFS1 0 0 1 1 PGFS0 0 1 0 1 Processing High when the frame sync is at the correct timing, low when not the correct timing. High when the frame sync is at the correct timing, low when continuously not the correct timing for 2ms or longer. High when the frame sync is at the correct timing, low when continuously not the correct timing for 4ms or longer. High when the frame sync is at the correct timing, low when continuously not the correct timing for 8ms or longer. These commands set the FOK signal hold time. See $3B for the FOK slice level. These are the values when MCK = 128Fs, and the hold time is inversely proportional to the MCK setting. PFOK1 0 0 1 1 PFOK0 0 1 0 1 Processing High when the RFDC value is higher than the FOK slice level, low when lower than the FOK slice level. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 4.35ms or more. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 10.16ms or more. High when the RFDC value is higher than the FOK slice level, low when continuously lower than the FOK slice level for 21.77ms or more. - 167 - CXD3048R MRS: MRT1, MRT0: This command switches the time constant for generating the MIRR comparator level of the MIRR generation circuit. When "0", the time constant is normal. (default) When "1", the time constant is longer than normal. The time during which MIRR = high due to the effects of RFDC signal pulse noise, etc., can be suppressed by setting MRS = 1. These commands limit the time while MIRR = high. MRT1 0 0 1 1 MRT0 0 1 0 1 : preset MIRR maximum time [ms] No time limit 1.10 2.20 4.00 $34A (preset: $34A 150) D15 1 D14 0 D13 1 D12 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 0 D1 0 D0 0 A/D COPY EMPH CAT DOUT DOUT DOUT WIN DOUT D b8 EN1 DMUT WOD EN EN2 SEL EN Command bit A/DSEL = 0 A/DSEL = 1 Command bit COPY EN = 0 COPY EN = 1 Command bit EMPH D = 0 EMPH D = 1 Command bit CAT b8 = 0 CAT b8 = 1 Command bit DOUT EN1 = 0 DOUT EN1 = 1 Processing Bit 1 of the channel status data is output as audio data. Bit 1 of the channel status data is output as other than audio data. Processing Bit 2 of the channel status data is output as digital copy prohibited. Bit 2 of the channel status data is output as digital copy enabled. Processing Bit 3 of the channel status data is output as without pre-emphasis. Bit 3 of the channel status data is output as with pre-emphasis. Processing Bit 8 of the channel status data is output as "0". Bit 8 of the channel status data is output as "1". Processing The DOUT signal, generated from the PCM data read out from the disc, is output. The DOUT signal, generated from the DA interface input, is output. - 168 - CXD3048R $34A commands cont. Command bit DOUT DMUT = 0 Digital Out output is normally output. DOUT DMUT = 1 All the audio data portions are output in zero, with Digital Out output as it is. Processing Command bit DOUT WOD = 0 The DOUT sync window is not open. DOUT WOD = 1 The DOUT sync window is open. Processing Command bit WIN EN = 0 WIN EN = 1 Processing Automatic synchronization to the input LRCK to match the phase with the internal processing is disabled. Automatic synchronization to the input LRCK to match the phase with the internal processing is disabled. Command bit DOUT EN2 = 0 DOUT EN2 = 1 Processing Set to "0" when not generating Digital Out from the DA interface input. Set to "1" when generating Digital Out from the DA interface input. DOUT EN1 0 0 0 0 0 0 0 0 0 1 DOUT DMUT -- -- -- -- -- -- -- -- -- 0 $B MD2 0 1 1 1 1 1 1 1 1 -- Other mute conditions -- 0 0 0 0 1 1 1 1 -- DOUT Mute -- 0 0 1 1 0 0 1 1 -- DOUT Mute F -- 0 1 0 1 0 1 0 1 -- DOUT output OFF 0dB The output from the PCM data read out from a disc. - dB The output from the PCM data read out from a disc. 0dB The output from the DA interface input. - dB The output from the DA interface input. --: don't care 1 1 -- -- -- -- See "Mute conditions" (1) and (3) to (5) of $AX commands for the other mute conditions. See $8 commands for DOUT Mute and DOUT Mute F. - 169 - CXD3048R $34B (preset: $34B 000) D15 1 D14 0 D13 1 D12 1 D11 D10 D9 0 D8 0 D7 D6 D5 D4 0 D3 0 D2 0 D1 0 D0 0 SFBK1 SFBK2 LB1SN LB2SN LB2SM The low frequency can be boosted for brake operation. See 5-12 for brake operation. SFBK1: When "1", brake operation is performed by setting the LowBooster-1 input to "0". This is valid only when TLB1ON = 1. Preset is "0". SFBK2: When "1", brake operation is performed by setting the LowBooster-2 input to "0". This is valid only when TLB2ON = 1. Preset is "0". See the $34C command booster setting for LB1SN, LB2SN and LB2SM. $34C (preset: $34C 000) D15 1 D14 1 D13 0 D12 0 D11 D10 D9 D8 D7 D6 0 D5 D4 D3 D2 D1 D0 THBON FHBON TLB1ON FLB1ON TLB2ON HBST1 HBST0 LB1S1 LB1S0 LB2S1 LB2S0 These bits turn on the boost function. (See 5-20. Filter Composition.) There are five boosters (three for the TRK filter and two for the FCS filter) which can be turned on and off independently. THBON: FHBON: TLB1ON: FLB1ON: TLB2ON: When "1", When "1", When "1", When "1", When "1", the the the the the high frequency is boosted for the TRK filter. Preset is "0". high frequency is boosted for the FCS filter. Preset is "0". low frequency is boosted for the TRK filter. Preset is "0". low frequency is boosted for the FCS filter. Preset is "0". low frequency is boosted for the TRK filter. Preset is "0". The difference between TLB1ON and TLB2ON is the position where the low frequency is boosted. For TLB1ON, the low frequency is boosted before the TRK jump, and for TLB2ON, after the TRK jump. The following commands set the boosters. (See 5-20. Filter Composition.) HBST1, HBST0: TRK and FCS HighBooster setting. HighBooster has the configuration shown in Fig. 5-22a, and can select three different combinations of coefficients BK1, BK2 and BK3. (See Table 5-23a.) An example of characteristics is shown in Fig. 5-24a. These characteristics are the same for both the TRK and FCS filters. The sampling frequency is 88.2kHz (when MCK = 128Fs). LB1S1, LB1S0, LB1SN: TRK and FCS LowBooster-1 setting. LowBooster-1 has the configuration shown in Fig. 5-22b, and can select six different combinations of coefficients BK4, BK5 and BK6. (See Table 5-23b.) An example of characteristics is shown in Fig. 5-24b. These characteristics are the same for both the TRK and FCS filters. The sampling frequency is 88.2kHz (when MCK = 128Fs). LB2S1, LB2S0, LB2SN, LB2SM: TRK LowBooster-2 setting. LowBooster-2 has the configuration shown in Fig. 5-22c, and can select six different combinations of coefficients BK7, BK8 and BK9. (See Table 5-23c.) An example of characteristics is shown in Fig. 5-24c. This booster is used exclusively for the TRK filter. The sampling frequency is 88.2kHz (when MCK = 128Fs). Note) Fs = 44.1kHz - 170 - CXD3048R BK3 Z -1 BK1 BK2 Z -1 HBST1 0 1 1 HBST0 -- 0 1 HighBooster setting BK1 -120/128 -124/128 -126/128 BK2 96/128 112/128 120/128 BK3 2 2 2 --: don't care Fig. 5-22a. Table. 5-23a. BK6 Z -1 BK4 BK5 Z -1 LB1S1 LB1S0 LB1SN 0 1 1 0 1 1 -- 0 1 -- 0 1 0 0 0 1 1 1 LowBooster-1 setting BK4 -255/256 -511/512 -1023/1024 -127/128 -255/256 -511/512 BK5 1023/1024 2047/2048 4095/4096 255/256 511/512 1023/1024 BK6 1/4 1/4 1/4 1 1 1 Characteristic diagram1 1 2 3 4 Fig. 5-22b. 5 6 Table. 5-23b. --: don't care BK9 Z -1 BK7 Z -1 BK8 LB2S1 LB2S0 LB2SN LB2SM 0 1 1 0 1 1 0 1 1 -- 0 1 -- 0 1 -- 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 LowBooster-2 setting BK7 -255/256 -511/512 -1023/1024 -31/32 -63/64 -127/128 -255/256 -511/512 -1023/1024 Table. 5-23c. BK8 1023/1024 2047/2048 4095/4096 127/128 255/256 511/512 1023/1024 2047/2048 4095/4096 BK9 1/4 1/4 1/4 1 1 1 1 1 1 Characteristic diagram1 1 2 3 4 5 6 Fig. 5-22c. 7 8 9 --: don't care 1 2 1 1 to to 6 9 correspond to correspond to 1 1 to to 6 9 in Fig. 5-23b respectively. in Fig. 5-23c respectively. - 171 - CXD3048R 15 12 9 3 6 3 2 1 Gain [dB] 0 -3 -6 -9 -12 -15 1 10 100 Frequency [Hz] 1k 10k +90 +72 3 2 1 +36 Phase [degree] 0 -36 -72 -90 1 10 100 Frequency [Hz] 1k 10k Fig. 5-24a. Servo HighBooster characteristics [FCS, TRK] (MCK = 128Fs) 1 HBST1 = 0 2 HBST1 = 1, HBST0 = 0 - 172 - 3 HBST1 = 1, HBST0 = 1 CXD3048R 15 12 9 6 3 6 5 4 Gain [dB] 0 -3 -6 -9 -12 -15 3 2 1 1 10 100 Frequency [Hz] 1k 10k 18 6 0 5 4 -18 Phase [degree] -36 -54 3 -72 2 1 -90 1 10 100 Frequency [Hz] 1k 10k Fig. 5-24b. Servo LowBooster-1 characteristics [FCS, TRK] (MCK = 128Fs) ( 1 to 6 correspond to 1 to 6 in Table 5-23b respectively.) - 173 - CXD3048R 15 9 12 9 6 3 Gain [dB] 8 7 6 5 4 0 -3 -6 -9 -12 -15 3 2 1 1 10 100 Frequency [Hz] 1k 10k 18 0 -18 Phase [degree] -36 -54 3 9 -72 2 8 1 7 6 5 4 -90 1 10 100 Frequency [Hz] 1k 10k Fig. 5-24c. Servo LowBooster-2 characteristics [TRK] (MCK = 128Fs) ( 1 to 9 correspond to 1 to 9 in Table 5-23c respectively.) - 174 - CXD3048R $34E (preset: $34E000) D15 1 IDFSL3: D14 1 D13 1 D12 0 D11 D10 D9 D8 D7 0 D6 D5 D4 D3 0 D2 0 D1 D0 IDFSL3 IDFSL2 IDFSL1 IDFSL0 DFSLS IDFT1 IDFT0 LPDF0 INVRFDC New DFCT detection output setting. When "0", only the DFCT signal described in 5-9 is detected and output from the DFCT pin. (default) When "1", the DFCT signal described in 5-9 and the new DFCT signal are switched and output from the DFCT pin. The switching timing is as follows. When the 5-9 DFCT signal is low, the new DFCT signal is output from the DFCT pin. When the 5-9 DFCT signal is high, this DFCT signal is output from the DFCT pin. In addition, the time at which the new DFCT signal can be output after the 5-9 DFCT signal switches to low can also be set. (See IDFT1 and IDFT0 of $34E.) IDFSL3 0 0 1 1 5-9 DFCT L H L H DFCT pin 5-9 DFCT 5-9 DFCT New DFCT 5-9 DFCT IDFSL2: IDFSL1: IDFSL0: DFSLS: IDFT1, IDFT0: New DFCT detection time setting. DFCT = high is held for a certain time after new DFCT detection. This command sets that time. When "0", a long hold time. (default) When "1", a short hold time. New DFCT detection sensitivity setting. When "0", a high detection sensitivity. (default) When "1", a low detection sensitivity. New DFCT release sensitivity setting. When "0", a high release sensitivity. (default) When "1", a low release sensitivity. DFCT slice level setting mode switching. When "0", the two bits of $3B commands SDF2 and SDF1 are used to set the DFCT slice level as usual. (default) When "1", the six bits of $3D commands SDF6 to SDF3 and $3B commands SDF2 and SDF1 are used to set the DFCT slice level. These commands set the time at which the new DFCT signal can be output (output prohibited time) after the 5-9 DFCT signal switches to low. IDFT1 0 0 1 1 IDFT0 0 1 0 1 : preset New DFCT signal output prohibited time 204.08s 294.78s 408.16s 612.24s LPDF0: INVRFDC: DFCT signal generation mode switching. When "0", the rise time constant of the DFCT generation circuit peak hold value is as usual. (default) When "1", the rise time constant of the DFCT generation circuit peak hold value is weighed. RFDC signal polarity inverted input setting. When "0", the RFDC signal polarity is set to non-inverted. (default) When "1", the RFDC signal polarity is set to inverted. - 175 - CXD3048R $34F D15 1 D14 1 D13 1 D12 1 D11 1 D10 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 -- FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 When D15 = D14 = D13 = D12 = D11 = 1 ($34F) D10 = 0 FBIAS LIMIT register write FBL9 to FBL1: Data; data compared with FB9 to FB1, FBL9 = MSB. When using the FBIAS register in counter mode, counter operation stops when the value of FB9 to FB1 matches with FBL9 to FBL1. D15 1 D14 1 D13 1 D12 1 D11 0 D10 1 D9 FB9 D8 FB8 D7 FB7 D6 FB6 D5 FB5 D4 FB4 D3 FB3 D2 FB2 D1 FB1 D0 -- When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 1 FBIAS register write FB9 to FB1: Data; two's complement data, FB9 = MSB. For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256 x VDD/4 and FB9 to FB1 = 100000000 to -256/256 x VDD/4 respectively. (VDD: supply voltage) D15 1 D14 1 D13 1 D12 1 D11 0 D10 0 D9 TV9 D8 TV8 D7 TV7 D6 TV6 D5 TV5 D4 TV4 D3 TV3 D2 TV2 D1 TV1 D0 TV0 When D15 = D14 = D13 = D12 = 1 ($34F) D11 = 0, D10 = 0 TRVSC register write TV9 to TV0: Data; two's complement data, TV9 = MSB. For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256 x VDD/4 and TV9 to TV0 = 1100000000 to -256/256 x VDD/4 respectively. (VDD: supply voltage) Notes) * When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to each bit TV8 to TV0 during external write are read out. * When reading out internally measured values and then writing these values externally, set TV9 the same as TV8. - 176 - CXD3048R $35 (preset: $35 58 2D) D15 FT1 D14 FT0 D13 FS5 D12 FS4 D11 FS3 D10 FS2 D9 FS1 D8 FS0 D7 FTZ D6 FG6 D5 FG5 D4 FG4 D3 FG3 D2 FG2 D1 FG1 D0 FG0 FT1, FT0, FTZ: Focus search-up speed Default value: 010 (0.673 x VDDV/s) Focus drive output conversion FT1 0 0 1 1 0 0 1 1 FT0 0 1 0 1 0 1 0 1 FTZ 0 0 0 0 1 1 1 1 Focus search speed [V/s] 1.35 x VDD 0.673 x VDD 0.449 x VDD 0.336 x VDD 1.79 x VDD 1.08 x VDD 0.897 x VDD 0.769 x VDD : preset, VDD: PWM driver supply voltage FS5 to FS0: Focus search limit voltage Default value: 011000 ((1 24/64) x VDD/2, VDD: PWM driver supply voltage) Focus drive output conversion AGF convergence gain setting value Default value: 0101101 FG6 to FG0: $36 (preset: $36 0E 2E) D15 D14 D13 D12 TJ4 D11 TJ3 D10 TJ2 D9 TJ1 D8 D7 D6 D5 TG5 D4 TG4 D3 TG3 D2 TG2 D1 TG1 D0 TG0 TDZC DTZC TJ5 TDZC: TJ0 SFJP TG6 DTZC: TJ5 to TJ0: SFJP: TG6 to TG0: Selects the TZC signal for generating the TRKCNCL signal during brake circuit operation. When "0", the edge of the HPTZC or STZC signal, whichever has the faster phase, is used. When "1", the edge of the HPTZC, STZC signal or the tracking drive signal zero-cross, whichever has the faster phase, is used. (See 5-12.) DTZC delay (8.5/4.25s, when MCK = 128Fs) Default value: 0 (4.25s) Track jump voltage Default value: 001110 ((1 14/64) x VDD/2, VDD: PWM driver supply voltage) Tracking drive output conversion Surf jump mode on/off The tracking PWM output is generated by adding the tracking filter output and TJReg (TJ5 to TJ0), by setting D7 to "1" (on) AGT convergence gain setting value Default value: 0101110 - 177 - CXD3048R $37 (preset: $37 50 BA) D15 D14 D13 D12 D11 SM3 D10 SM2 D9 SM1 D8 D7 D6 D5 D4 D3 D2 D1 D0 FZSH FZSL SM5 SM4 FZSH, FZSL: SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT FZC (Focus Zero Cross) slice level Default value: 01 (1/8 x VDD/2, VDD: supply voltage); FE input conversion FZSH 0 0 1 1 FZSL 0 1 0 1 Slice level 1/4 x VDD/2 1/8 x VDD/2 1/16 x VDD/2 1/32 x VDD/2 : preset SM5 to SM0: AGS: AGJ: AGGF: AGGT: Sled move voltage Default value: 010000 ((1 16/64) x VDD/2, VDD: PWM driver supply voltage) Sled drive output conversion AGCNTL self-stop on/off Default value: 1 (on) AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms, when MCK = 128Fs) Default value: 0 (63ms) Focus AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) Tracking AGCNTL internally generated sine wave amplitude (small/large) Default value: 1 (large) FE/TE input conversion AGGF AGGT 0 (small) 1/32 to VDD/2 1 (large) 1/16 to VDD/2 0 (small) 1/16 to VDD/2 1 (large) 1/8 to VDD/2 : preset AGV1: AGV2: AGHS: AGHT: AGCNTL convergence sensitivity during high sensitivity adjustment; high/low Default value: 1 (high) AGCNTL convergence sensitivity during low sensitivity adjustment; high/low Default value: 0 (low) AGCNTL high sensitivity adjustment on/off Default value: 1 (on) AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs) Default value: 0 (256ms) - 178 - CXD3048R $38 (preset: $38 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0 DC offset cancel. See 5-3. VCLM: VC level measurement (on/off) VCLC: VC level compensation for FCS In register (on/off) FLM: Focus zero level measurement (on/off) FLC0: Focus zero level compensation for FZC register (on/off) RFLM: RF zero level measurement (on/off) RFLC: RF zero level compensation (on/off) Automatic gain control. See 5-6. AGF: Focus auto gain adjustment (on/off) AGT: Tracking auto gain adjustment (on/off) Misoperation prevention circuit DFSW: Defect disable switch (on/off) Setting this switch to "1" (on) disables the defect countermeasure circuit. LKSW: Lock switch (on/off) Setting this switch to "1" (on) disables the sled free-running prevention circuit. DC offset cancel. See 5-3. TBLM: Traverse center measurement (on/off) TCLM: Tracking zero level measurement (on/off) FLC1: Focus zero level compensation for FCS In register (on/off) TLC2: Traverse center compensation (on/off) TLC1: Tracking zero level compensation (on/off) TLC0: VC level compensation for TRK/SLD In register (on/off) Note) Commands marked with are accepted every 2.9ms. (when MCK = 128Fs) All commands are on when "1". - 179 - CXD3048R $39 (preset: $390000) D15 DAC D14 SD6 D13 SD5 D12 SD4 D11 SD3 D10 SD2 D9 SD1 D8 SD0 When $3A command SVDA = 0 DAC: Serial data readout DAC mode setting. When "0", serial data cannot be read out. (default) When "1", serial data can be read out. SD6 to SD0: These bits select the serial readout data. D14 SD6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 D13 SD5 D12 SD4 D11 SD3 D10 SD2 D9 SD1 D8 SD0 Readout data Coefficient RAM data Data RAM data 1 0 1 0 0 1 0 1 -- -- -- 1 0 1 0 RF AVRG register RFDC input signal FCS Bias register TRVSC register DFCT count RFDC (Bottom) RFDC (Peak) RFDC (Peak - Bottom) VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal Readout data length 8 bits 16 bits 8 bits 8 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits 9 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits --: don't care Note) When $3A SVDA is changed, select the readout data again. Coefficient RAM address Data RAM address 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 1 1 0 -- -- -- 1 1 0 0 - 180 - CXD3048R When $3A command SVDA = 1 DAC: This command selects whether to set readout data for the left or right channel. When "0", right channel readout data is selected. (default) When "1", left channel readout data is selected. SD6 to SD0: These bits select the data to be output from the left or right channel. D14 SD6 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 0 D13 SD5 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 D12 SD4 D11 SD3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 D10 SD2 1 1 1 1 0 0 1 0 1 1 1 0 0 0 0 D9 SD1 1 1 0 0 1 0 0 0 1 1 0 1 1 0 0 D8 SD0 1 0 1 0 0 0 0 0 1 0 0 1 0 1 0 Readout data Data RAM data RF AVRG register RFDC input signal FCS Bias register TRVSC register FCS output signal TRK output signal VC AVRG register FE AVRG register FE (A-B): FCS in Reg TE (E-F): TRK in Reg TE AVRG register FE input signal TE input signal SE input signal VC input signal Readout data length 16 bits 8 bits 8 bits 9 bits 9 bits 8 bits 8 bits 9 bits 9 bits 9 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits Data RAM address 1 Right channel preset 2 Left channel preset Note) Coefficient RAM data cannot be output from the audio DAC side. Do not output RFDC (peak, bottom, peak-bottom) or the DFCT count from the audio DAC side. When $3A SVDA is changed, select the readout data again. The DFCT count counts the number of times the DFCT signal rises while $3994 is set. Readout outputs the DFCT count at that time. Memory Readout The following three memories can be readout without waiting the memory access. * M02 (Sled filter final memory) * M12 (Focus hold filter final memory) * M1A (Track hold filter final memory) - 181 - CXD3048R $3A (D15 = 0) (preset: $3A0000) D15 0 FBON: FBSS FBUP D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FBON FBSS FBUP FBV1 FBV0 FIFZC TJD0 FPS1 FPS0 TPS1 TPS0 SVDA SJHD INBK MTI0 FBIAS (focus bias) register operation setting. FBON 0 1 1 1 FBSS 0 0 1 1 FBUP -- -- 0 1 Processing FBIAS (focus bias) register addition off. FBIAS (focus bias) register addition on. FBIAS register acts as a down counter. FBIAS register acts as an up counter. FBV1, FBV0: --: don't care FBIAS (focus bias) counter voltage switching. The number of FCS BIAS count-up/-down steps per cycle is decided by these bits. FBV1 0 0 1 1 FBV0 0 1 0 1 Number of steps per cycle 1 2 4 8 The counter changes once for each sampling cycle of the focus servo filter. When MCK is 128Fs, the sampling frequency is 88.2kHz. When converted to FE input, 1 step is approximately 1/29 x VDD/2, VDD = supply voltage. FIFZC: TJDO: FPS1, FPS0: TPS1, TPS0: : preset This selects the FZC slice level setting command. When "0", the FZC slice level is determined by the $37 FZSH and FZSL setting values. (default) When "1", the FZC slice level is determined by the $3F8 FIFZB3 to FIFZB0 and FIFZA3 to FIFZA0 setting values. This allows more detailed setting and the addition of hysteresis compared to the $37 FZSH and FZSL setting. This sets the tracking servo filter data RAM to "0" when switched from track jump to servo on only when SFJP = 1 (during surf jump operation). Gain setting when transferring data from the focus filter to the PWM block. Gain setting when transferring data from the tracking filter to the PWM block. These are effective for increasing the overall gain in order to widen the servo band, etc. Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However, 6dB, 12dB and 18dB can be selected independently for focus and tracking by setting the relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00. FPS1 0 0 1 1 FPS0 0 1 0 1 Relative gain 0dB +6dB +12dB +18dB TPS1 0 0 1 1 TPS0 0 1 0 1 Relative gain 0dB +6dB +12dB +18dB : preset SVDA: SJHD: INBK: MTI0: This allows the data set by the $39 command to be output through the audio DAC. When "0", audio is output. (default) When "1", the data set by the $39 command is output. This holds the tracking filter output at the value when surf jump starts during surf jump. When INBK = 0 (off), the brake circuit masks the tracking drive signal with the TRKCNCL signal which is generated by taking the MIRR signal at the TZC edge. When INBK = 1 (on), the tracking filter input is masked instead of the drive output. The tracking filter input is masked when the MIRR signal is high by setting MTI0 = 1 (on). - 182 - CXD3048R $3A8 (preset : $3A 80 00) D15 1 D14 0 D13 0 D12 0 D11 D10 D9 D8 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 FPGS1 FPGS0 TPGS1 TPGS0 FPGS1, FPGS0: These increase +6dB, +12dB and +18dB immediately before FCS SRCH. TPGS1, TPGS0: These increase +6dB, +12dB and +18dB immediately before TRK JMP. FPGS1 FPGS0 0 0 1 1 0 1 0 1 Gain 0dB +6dB +12dB +18dB : preset TPGS1 TPGS0 0 0 1 1 0 1 0 1 Gain 0dB +6dB +12dB +18dB : preset $3A9 (preset : $3A 90 00) D15 1 UDFZC: D14 0 D13 0 D12 1 D11 0 D10 0 D9 0 D8 0 D7 UDFZC D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 This detects FZC not depending on the search direction. When "0", FZC is detected for UP search. (conventional system: default) When "1", FZC is detected not depending on the search direction. $3AFF (preset : $3A FF 00) D15 1 D14 1 D13 1 D12 1 D11 1 D10 1 D9 1 D8 1 D7 0 D6 0 D5 0 D4 0 D3 D2 D1 0 D0 0 SRQ1 SRQ0 SRQ1, SRQ0: These bits select the ASYO output delay time. SRQ1 0 0 1 1 SRQ0 0 1 0 1 ASYO output delay time Approx. 0ns Approx. 5ns Approx. 10ns Approx. 15ns : preset - 183 - CXD3048R $3B (preset: $3B E0 50) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 0 D1 0 D0 0 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT SFOX, SFO2, SFO1: FOK slice level Default value: 011 (28/256 x VDD/2, VDD = supply voltage) RFDC input conversion SFOX 0 0 0 0 1 1 1 1 SFO2 0 0 1 1 0 0 1 1 SFO1 0 1 0 1 0 1 0 1 Slice level 16/256 20/256 24/256 28/256 32/256 40/256 48/256 56/256 x VDD/2 x VDD/2 x VDD/2 x VDD/2 x VDD/2 x VDD/2 x VDD/2 x VDD/2 : preset SDF2, SDF1: DFCT slice level Default value: 10 (0.0313 x VDD) RFDC input conversion SFO2 0 0 1 1 SFO1 0 1 0 1 Slice level 0.0156 0.0234 0.0313 0.0391 x VDD x VDD x VDD x VDD : preset, VDD: supply voltage See the $34E command DFSLS and $3D commands SDF6 to SDF3. MAX2, MAX1: DFCT maximum time (MCK = 128Fs) Default value: 00 (no timer limit) MAX2 * 0 0 1 1 MAX1 0 1 0 1 DFCT maximum time No timer limit 2.00ms 2.36ms 2.72ms : preset BTF: Bottom hold double-speed count-up mode for MIRR signal generation On/off (default: off) On when "1". - 184 - CXD3048R D2V2, D2V1: Peak hold 2 for DFCT signal generation Count-down speed setting Default value: 01 (0.086 x VDD/ms, 44.1kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. Count-down speed D2V2 0 0 1 1 D2V1 0 1 0 1 [V/ms] 0.0431 x VDD 0.0861 x VDD 0.172 x VDD 0.344 x VDD [kHz] 22.05 44.1 88.2 176.4 : preset, VDD: supply voltage D1V2, D1V1: Peak hold 1 for DFCT signal generation Count-down speed setting Default value: 01 (0.688 x VDD/ms, 352.8kHz) [V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter. Count-down speed D1V2 0 0 1 1 D1V1 0 1 0 1 [V/ms] 0.344 x VDD 0.688 x VDD 1.38 x VDD 2.75 x VDD [kHz] 176.4 352.8 705.6 1411.2 : preset, VDD: supply voltage RINT: This initializes the initial-stage registers of the circuits which generate MIRR, DFCT and FOK. - 185 - CXD3048R $3C (preset: $3C 00 80) D15 D14 D13 D12 D11 D10 D9 D8 0 D7 D6 D5 D4 D3 0 D2 0 D1 0 D0 0 COSS COTS CETZ CETF COT2 COT1 MOT2 COSS, COTS: BTS1 BTS0 MRC1 MRC0 These select the TZC signal used when generating the COUT signal. COSS 1 0 0 COTS -- 0 1 TZC STZC HPTZC DTZC : preset, --: don't care STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs) DTZC is the delayed phase STZC. (The delay time can be selected by D14 of $36.) HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz. See 5-13. CETZ: Normally, the input from the TE pin enters the TRK filter and is used to generate the TZC signal. However, the input from the CE pin can also be used. This function is for the center error servo. When "0", the TZC signal is generated by using the signal input to the TE pin. When "1", the TZC signal is generated by using the signal input to the CE pin. When "0", the signal input to the TE pin is input to the TRK servo filter. When "1", the signal input to the CE pin is input to the TRK servo filter. CETF: These commands output the TZC signal. COT2, COT1: The COUT signal is replaced by the TZC signal. Concretely, the TZC signal is output from the COUT pin and the TZC signal is used for auto sequence instead of the COUT signal. COT2 1 0 0 COT1 -- 1 0 COUT pin output STZC HPTZC COUT : preset, --: don't care MOT2: The MIRR signal is replaced by the STZC signal. Concretely, the STZC signal is output from the MIRR pin and the STZC signal is used for generating the COUT signal instead of the MIRR signal. These commands set the MIRR signal generation circuit. BTS1, BTS0: These set the count-up speed for the bottom hold value of the MIRR generation circuit. The time per step is approximately 708ns (when MCK = 128Fs). The preset value is BTS1 = 1, BTS0 = 0 like the CXD2586R. These bits are valid only when BTF of $3B is "0". MRC1, MRC0: These set the minimum pulse width for masking the MIRR signal of the MIRR generation circuit. As noted in 5-9, the MIRR signal is generated by comparing the waveform obtained by subtracting the bottom hold value from the peak hold value with the MIRR comparator level. Strictly speaking, however, for MIRR to become high, these levels must be compared continuously for a certain time. These bits set that time. The preset value is MRC1 = 0, MRC0 = 0 like the CXD2586R. BTS1 0 0 1 1 BTS0 0 1 0 1 Number of count-up steps per cycle 1 2 4 8 - 186 - MRC1 MRC0 Setting time [s] 0 0 5.669 0 1 11.338 1 0 22.675 1 1 45.351 : preset (when MCK = 128Fs) CXD3048R $3D (preset: $3D 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 0 D2 0 D1 0 D0 0 SFID SFSK THID THSK ABEF TLD2 TLD1 TLD0 SDF6 SDF5 SDF4 SDF3 SFID: SFSK: THID: THSK: ABEF: TLD2 to TLD0: SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When the low frequency component of the tracking error signal obtained from the RF amplifier is attenuated, the low frequency can be amplified and input to the SLD servo filter. Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally, the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to M00 can be kept uniform by adjusting the K30 value even during the above switching. TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK filter second-stage output. When signals other than the tracking error signal from the RF amplifier are input to the SE input pin, the signal transmitted from the TE pin can be obtained as TRK hold filter input. Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally, the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to M18 can be kept uniform by adjusting the K46 value even during the above switching. See "5-20. Filter Composition" regarding the SFID, SFSK, THID and THSK commands. The focus error (FE) and tracking error (TE) can be generated internally. When 0, the FE and TE signal input mode results. Input each error signal through the FE and TE pins. (default) When 1, the FE and TE signal generation mode results and the FE and TE signals are generated internally. These turn on and off SLD filter correction independently of the TRK filter. See $38 (TLC0 to TLC2) and Fig. 5-3. TLC2 0 1 TLD2 -- 0 1 TLD1 -- 0 1 Traverse center correction TRK filter OFF ON ON SLD filter OFF ON OFF TLC1 0 1 Tracking zero level correction TRK filter OFF ON ON SLD filter OFF ON OFF TLC0 0 1 TLD0 -- 0 1 VC level correction TRK filter OFF ON ON SLD filter OFF ON OFF : preset, --: don't care - 187 - CXD3048R SDF6 to SDF3: These set the DEFECT slice level when the $34E command DFSLS = 1. SDF6 to SDF1 111111 111110 111101 : Slice level 63/256 x VDD/2 62/256 x VDD/2 61/256 x VDD/2 : 2/256 x VDD/2 1/256 x VDD/2 0 : preset 000010 000001 000000 Note) Set SDF2 and SDF1 with the $3B command. * Input coefficient sign inversion when SFID = 1 and THID = 1 The preset coefficients for the TRK filter are negative for input and positive for output. With this, the CXD3048R outputs servo drives which have the reversed phase of input errors. Negative input coefficient TE K19 TRK filter Positive output coefficient K22 Negative input coefficient SE K00 SLD filter Positive output coefficient K05 Positive input coefficient TRK Hold K40 TRK Hold filter Positive output coefficient K45 When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so the SLD input coefficient (K00) sign must be inverted. (For example, inverting the sign for coefficient K00: E0h results in 20h.) For the same reason, when THID = 1, the TRK hold input coefficient (K40) sign must be inverted. Negative input coefficient TE K19 TRK filter M0D Positive output coefficient K22 Positive input coefficient SE K00 SLD filter Positive output coefficient K05 Negative input coefficient TRK Hold K40 TRK Hold filter Positive output coefficient K45 For TRK servo gain normal See "5-20. Filter Composition". - 188 - CXD3048R $3E (preset: $3E 00 00) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 0 D4 D3 D2 D1 D0 F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD F1NM, F1DM: LKIN COIN MDFI MIRI XT1D T1NM, T1UM: F3NM, F3DM: T3NM, T3UM: Quasi double accuracy setting for FCS servo filter first-stage On when "1"; default is "0". F1NM: Gain normal F1DM: Gain down Quasi double accuracy setting for TRK servo filter first-stage On when "1"; default is "0". T1NM: Gain normal T1UM: Gain up Quasi double accuracy setting for FCS servo filter third-stage On when "1"; default is "0". Generally, the advance amount of the phase increases by partially setting the FCS servo third-stage filter which is used as the phase compensation filter to double accuracy. F3NM: Gain normal F3DM: Gain down Quasi double accuracy setting for TRK servo filter third-stage On when "1"; default is "0". Generally, the advance amount of the phase increases by partially setting the TRK servo third-stage filter which is used as the phase compensation filter to double accuracy. T3NM: Gain normal T3UM: Gain up Note) Filter first- and third-stage quasi double accuracy settings can be set individually. See "5-20 Filter Composition" at the end of this specification concerning quasi double accuracy. DFIS: FCS hold filter input extraction node selection 0: M05 (Data RAM address 05); default 1: M04 (Data RAM address 04) This command masks the TLC2 command set by D2 of $38 only when FOK is low. On when "1"; default is "0". When "0", the internally generated LOCK signal is output to the LOCK pin. (default) When "1", the LOCK signal can be input from an external source to the LOCK pin. When "0", the internally generated COUT signal is output to the COUT pin. (default) When "1", the COUT signal can be input from an external source to the COUT pin. TLCD: LKIN: COIN: The MIRR, DFCT and FOK signals can also be input from an external source. MDFI: When "0", the MIRR, DFCT and FOK signals are generated internally. (default) When "1", the MIRR, DFCT and FOK signals can be input from an external source through the MIRR, DFCT and FOK pins. MIRI: When "0", the MIRR signal is generated internally. (default) When "1", the MIRR signal can be input from an external source through the MIRR pin. MDFI 0 0 1 XT1D: MIRI 0 1 -- MIRR, DFCT and FOK are all generated internally. MIRR only is input from an external source. MIRR, DFCT and FOK are all input from an external source. : preset, --: don't care The input to the servo master clock is used without being frequency-divided by setting XT1D to "1". This command takes precedence over the XTSL pin, XT2D and XT4D. See the description of $3F for XT2D and XT4D. - 189 - CXD3048R $3F (preset: $3F 00 10) D15 0 AGG4: D14 D13 D12 D11 0 D10 D9 D8 D7 0 D6 D5 D4 1 D3 SRO1 D2 0 D1 D0 AGG4 XT4D XT2D DRR2 DRR1 DRR0 ASFG FTQ AGHF ASOT This varies the amplitude of the internally generated sine wave using the AGGF and AGGT commands during AGC. When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below. Sine wave amplitude AGG4 AGGF AGGT 0 0 1 -- -- 0 1 0 1 1 -- -- 0 1 0 1 0 1 FE input conversion 1/32 x VDD/2 1/16 x VDD/2 -- -- TE input conversion -- -- 1/16 x VDD/2 1/8 x VDD/2 1/64 x VDD/2 1/32 x VDD/2 1/16 x VDD/2 1/8 x VDD/2 : preset, --: don't care See $37 for AGGF and AGGT. The presets are AGG4 = 0, AGGF = 1 and AGGT = 1. XT4D, XT2D: MCK (digital servo master clock) frequency division ratio setting This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is generated. See the description of $3E for XT1D. Also, see "5-2. Digital Servo Block Master Clock (MCK)". XT1D 0 1 0 0 XT2D 0 -- 1 0 XT4D 0 -- -- 1 Frequency division ratio According to XTSL 1/1 1/2 1/4 : preset, --: don't care DRR2 to DRR0: Partially clears the Data RAM values ("0" write). The following values are cleared when "1" (on) respectively; default is "0". DRR2: M08, M09, M0A DRR1: M00, M01, M02 DRR0: M00, M01, M02 only when LOCK = low Note) Set DRR1 and DRR0 on for 50s or more. ASFG: When vibration detection is performed during anti-shock circuit operation, the FCS servo filter is forcibly set to gain normal status. On when "1"; default is "0". FTQ: The slope of the output during focus search is 1/4 the conventional output slope. On when "1"; default is "0". - 190 - CXD3048R SRO1: This command is used to continuously externally output various data inside the digital servo block which have been specified with the $39 command. (However, D15 (DAC) of $39 must be set to "1".) Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by setting this command to "1". SRO1 = 1 SOLK XOLT SOUT Output from XPCK pin. Output from GFS pin. Output from XUGF pin. AGHF: ASOT: This halves the frequency of the internally generated sine wave during AGC. The anti-shock signal, which is internally detected, is output from the ATSK pin. Output when "1"; default is "0". Vibration detection when a high signal is output for the anti-shock signal output. - 191 - CXD3048R $3F8 (preset: $3F8800) D15 1 D14 0 D13 0 D12 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SYG3 SYG2 SYG1 SYG0 FIFZB3 FIFZB2 FIFZB1 FIFZB0 FIFZA3 FIFZA2 FIFZA1 FIFZA0 SYG3 to SYG0: These simultaneously set the focus drive, tracking drive and sled drive output gains. See the $AF and $CX commands for the spindle drive output gain setting. SYG3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SYG2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SYG1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SYG0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GAIN 0 (- dB) 0.125 (-18.1dB) 0.250 (-12.0dB) 0.375 (-8.5dB) 0.500 (-6.0dB) 0.625 (-4.1dB) 0.750 (-2.5dB) 0.875 (-1.2dB) 1.000 (0.0dB) 1.125 (+1.0dB) 1.250 (+1.9dB) 1.375 (+2.8dB) 1.500 (+3.5dB) 1.625 (+4.2dB) 1.750 (+4.9dB) 1.875 (+5.5dB) : preset FIFZB3 to FIFZB0: This sets the slice level at which FZC changes from high to low. FIFZA3 to FIFZA0: This sets the slice level at which FZC changes from low to high. The FIFZB3 to FIFZB0 and FIFZA3 to FIFZA0 setting values are valid only when $3A FIFZC is "1". Set so that the FIFZB3 to FIFZB0 FIFZA3 to FIFZA0. Hysteresis can be added to the slice level by setting FIFZB3 to FIFZB0 < FIFZA3 to FIFZA0. FZC slice level = FIFZB3 to FIFZB0 or FIFZA3 to FIFZA0 setting value x 0.5 x VDD [V] 32 - 192 - CXD3048R $3F9 (preset: $3F9000) D15 1 D14 0 D13 0 D12 1 D11 D10 D9 0 D8 1 D7 0 D6 0 D5 D4 D3 D2 D1 D0 FSUD FFSUP FFS5 FFS4 FFS3 FFS2 FFS1 FFS0 FSUD, FFSUP: These set the focus search type. The focus search is started by the $47 command. FSUD 0 0 1 FFSUP 0 1 0 Focus search type The usual focus search is performed. UP search is performed, and the focus servo is turned on at the FZC falling edge. Do not set. When the upper limit value is reached during the focus search, the focus search stops. After that, when the lower limit value is reached UP/DOWN search is performed. These limit values should be set with the $35 FS5 to FS0. When the lower limit value is reached during the focus search, the focus search stops. After that, when the upper limit value is reached UP/DOWN search is performed. These limit values should be set with the $35 FS5 to FS0. : preset 1 1 FFS5 to FFS0: These set the focus search amplitude voltage. Valid only when FSUD = 1. Focus search amplitude = (1 FFS5 to FFS0 setting values ) x 0.5 x VDD [V] 64 - 193 - CXD3048R Description of Data Readout 64 SOCK (5.6448MHz) XOLT (88.2kHz) MSB 8-bit data MSB SOUT MSB 16-bit data 9-bit data LSB LSB LSB ... 32 ... 16 8 1 16-bit register for serial/parallel conversion SOUT LSB 16-bit register for latch LSB To the 7-segment LED * * * * * * To the 7-segment LED MSB SOCK CLK CLK MSB Data is connected to the 7-segment LED by 4-bits at a time. This enables Hex display using four 7-segment LEDs. XOLT SOUT Serial data input D/A SOCK XOLT Clock input Latch enable input Analog output Offset adjustment, gain adjustment To an oscilloscope, etc. Waveforms can be monitored with an oscilloscope using a serial input-type D/A converter as shown above. - 194 - CXD3048R 5-19. List of Servo Filter Coefficients Fix indicates that normal preset values should be used. - 195 - CXD3048R - 196 - 5-20. Filter Composition The internal filter composition is shown below. K: Coefficient RAM address, M: Data RAM address FCS Servo Gain Normal fs = 88.2kHz FCS Hold Reg2 FCS In Reg Sin ROM 2-1 AGFON K06 DFCT M03 K06 Z -1 K08 K0F M04 Z -1 K09 K0A 2 -7 K0B 2 -7 K0D 27 M1F To FCS Hold K0F M05 Z -1 K0C K0E M1E To FCS Hold M06 Z -1 K10 K11 FCS AUTO Gain M07 K13 Note) Set the MSB bit of the K0B and K0D coefficients to "0". FCS Servo Gain Down fs = 88.2kHz FCS Hold Reg2 FCS In Reg 2 -1 DFCT M03 K06 Z -1 K24 Z -1 K25 K26 2 -7 K27 2 -7 K29 K28 Z -1 K2A Z -1 K2C K2B M04 M1F To FCS Hold K2B M05 M1E To FCS Hold M06 K2D FSC AUTO Gain M07 K13 - 197 - Note) Set the MSB bit of the K27 and K29 coefficients to "0". FPS1, 0 FPGS1, 0 BK3 Z -1 BK1 Z -1 BK2 BK6 Z -1 BK4 Z -1 FCS SRCH BK5 PWM CXD3048R TRK Servo Gain Normal fs = 88.2kHz TRK Hold Reg TRK In Reg Sin ROM 2-1 AGTON K19 DFCT K19 M0B Z -1 K1A K1B M0C Z -1 K1C 2 K1D -7 To SLD Servo, TRK Hold M0D Z -1 K1E 2 -7 TRK AUTO Gain M0E Z -1 K22 M0F K23 K20 K21 K1F Note) Set the MSB bit of the K1D and K1F coefficients to "0". TRK Servo Gain Up1 fs = 88.2kHz TRK Hold Reg TRK In Reg 2 -1 DFCT K19 M0B Z -1 K1A M0C Z -1 K1B K3C M0E Z -1 K3D K3E TRK AUTO Gain M0F K23 27 - 198 - TRK Servo Gain Up2 fs = 88.2kHz TRK Hold Reg TRK In Reg 2 -1 DFCT K19 Z M0B -1 TRK AUTO Gain M0C Z -1 K36 K37 K38 2 -7 K39 2 -7 K3B M0D Z -1 K3A K3C K3D M0E Z -1 K3E M0F K23 Note) Set the MSB bit of the K39 and K3B coefficients to "0". TPS1, 0 TPGS1, 0 BK3 Z -1 BK1 BK2 Z -1 BK6 BK9 Z -1 BK4 Z -1 TRK JMP BK5 BK7 Z -1 Z -1 BK8 PWM CXD3048R FCS Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EAXX0) M1F FCS Hold Reg 2 FCS In Reg Sin ROM 2 -1 AGFON K06 DFCT K06 M03 Z -1 81H 2 -7 K08 2 -7 K09 K0B 7FH K0F M04 Z -1 K0A 2 -7 2 K0D K0E To FCS Hold M1E K0F M05 Z -1 K0C 80H 2 -7 27 K10 To FCS Hold M06 Z -1 K11 FCS AUTO Gain M07 K13 Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K0B, K09 and K0E coefficients during quasi double accuracy to "0". FCS Servo Gain Down; fs = 88.2kHz, during quasi double accuracy (Ex.: $3E5XX0) M1F FCS Hold Reg 2 K2B DFCT 2 -1 K06 M03 Z -1 81H 2 -7 K24 2 -7 K25 K27 7FH M04 Z -1 K26 2 -7 2 -7 K29 K2A To FCS Hold M1E K2B M05 Z -1 K28 80H 2 -7 To FCS Hold M06 Z -1 K2C K2D FCS AUTO Gain M07 K13 - 199 - FCS In Reg Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25 and K2A coefficients during quasi double accuracy to "0". 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. FPS1, 0 FPGS1, 0 BK3 Z -1 BK1 BK2 Z -1 BK6 PWM Z -1 BK4 BK5 Z -1 FCS SRCH CXD3048R TRK Servo Gain Normal; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EXAX0) TRK Hold Reg TRK In Reg Sin ROM 2 -1 AGTON K19 DFCT M0B K19 Z -1 81H 2 -7 K1A 2 -7 K1B K1D Z -1 7FH K1C 2 -7 2 -7 K1F K20 Z -1 K1E 80H 2 -7 Z -1 K21 M0C M0D M0E K22 TRK AUTO Gain M0F K23 Note) Set the MSB bit of the K1D and K1F coefficirnts during normal operation, and of the K1A, K1B and K20 coefficients during quasi double accuracy to "0". TRK Servo Gain Up1; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0) TRK Hold Reg TRK In Reg 2 -1 DFCT K19 M0B Z -1 81H 2 -7 K1A 2 -7 K1B K3C M0C Z -1 7FH 80H 2 -7 M0E Z -1 K3D K3E TRK AUTO Gain M0F 27 K23 - 200 - Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to "0". TRK Servo Gain Up2; fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0) TRK Hold Reg TRK In Reg 2 -1 DFCT K19 M0B Z -1 81H 2 -7 K36 2 -7 K37 K39 M0C Z -1 7FH K38 2 -7 2 -7 K3B K3C M0D Z -1 K3A 80H 2 -7 M0E K3E Z -1 K3D TRK AUTO Gain M0F K23 Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and of the K36, K37 and K3C coefficients during quasi double accuracy to "0". 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy. TPS1, 0 TPGS1, 0 BK3 Z -1 BK6 Z -1 BK4 Z -1 TRK JMP BK5 BK9 Z -1 BK7 Z -1 PWM Z -1 BK1 BK2 CXD3048R BK8 CXD3048R SLD Servo fs = 345Hz TRK SERVO FILTER Secont-stage output K30 M0D 2 -1 SFID K00 Z -1 K01 2 -7 K02 2 -7 K04 K03 Z -1 SLD MOV SFSK (only when TGup2 is used.) M00 M01 K05 TRK AUTO Gain M02 27 K07 PWM SLD In Reg Note) Set the MSB bit of the K02 and K04 coefficients to "0". HPTZC/Auto Gain fs = 88.2kHz 2 -1 Slice AGFON 2 -1 AGTON AGFON M08 Z -1 K14 K15 M09 Z -1 M0A Z -1 K17 Slice AUTO Gain Reg TZC Reg FCS In Reg TRK In Reg Sin ROM - 201 - CXD3048R Anti Shock fs = 88.2kHz 2 -1 TRK In Reg K12 M08 Z -1 M09 Z -1 K31 K16 2 -7 K34 K33 M0A Z -1 Anti Shock Reg K35 Comp Note) Set the MSB bit of the K34 coefficient to "0". The comparator level is 1/16 the maximum amplitude of the comparator input. AVRG fs = 88.2kHz 2 -1 VC, TE, FE, RFDC 2 -7 M08 Z -1 AVRG Reg TRK Hold fs = 345Hz TRK SERVO FILTER Second-stage output K46 M0D 2 -1 THID K40 Z -1 K41 2 -7 K42 2 -7 K44 K43 Z -1 THSK (only when TGup2 is used.) M18 SLD In Reg M19 K45 TRK Hold Reg Note) Set the MSB bit of the K42 and K44 coefficients to "0". FCS Hold fs = 345Hz FCS SERVO FILTER First-stage output M04 DFIS ($3E) K2B M1F K2B when using the FCS Gain Down filter M10 Z -1 K49 2 -7 K4A 2 -7 K4C K4B M11 Z -1 K4D M12 FCS Hold Reg 2 M05 FCS SERVO FILTER Second-stage output K0F K48 M1E Note) Set the MSB bit of the K4A and K4C coefficients to "0". - 202 - CXD3048R 5-21. TRACKING and FOCUS Frequency Response Tracking frequency response 40 NORMAL GAIN UP 30 90 180 G - Gain [dB] 20 G 0 10 -90 0 -10 2.1 10 100 f - Frequency [Hz] 1k -180 20k When using the preset coefficients with the boost function off. Focus frequency response 40 NORMAL GAIN DOWN 30 90 20 180 G 0 10 -90 0 -10 2.1 10 100 f - Frequency [Hz] 1k -180 20k When using the preset coefficients with the boost function off. - 203 - - Phase [degree] G - Gain [dB] - Phase [degree] [6] Application Circuit TD DOUT ATSK DOUT COUT XUGF XPCK GFS LRMU LRMU C2PO MIRR DFCT DFCT FD VCC GND RFO FZC FE TE CE VC 91 SE 92 FE 93 VC 94 VSS2 95 FRDR 96 FFDR Vcc SSTP SLED SPDL GND MDS Driver setting 97 TRDR 98 TFDR 99 SRDR 100 SFDR 101 SSTP 102 MDS 103 MDP C176 104 C176 105 VDD2 106 LRCK 107 LRCKI 108 PCMD 109 PCMDI 110 BCK 111 BCKI 112 DVDD 113 A3 114 A2 115 A1 VCC VSS XRAS XCAS XWE XOE A11 to A0 D3 to D0 4M DRAM or 16M DRAM 116 A0 117 A10 118 A11 119 TEST3 TEST1 TEST2 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RFDC VPCO XPCK IGEN RFAC BIAS TE ASYI VCTL CE ASYO VDD1 AVSS0 AVDD0 AVDD3 AVSS3 CLTV GFS XUGF C2PO FILO COUT FILI MIRR PCO FOK FOK VSS1 60 TEST 59 TES1 58 AVDD2 57 AOUT2 56 VREFR 55 AVSS2 54 AVSS1 53 VREFL 52 AOUT1 51 AVDD1 50 XVSS 49 XTAO 48 XTAI 47 XVDD 46 CXD3048R HVDD 45 HPR 44 HPL 43 HVSS 42 XTSL 41 EXCK 40 SBSO 39 XWIH 38 XEMP 37 SQSO 36 SCLK 35 SQCK 34 VSS0 33 R4M 32 WDCK WFCK PWMI XRST XQOK SCOR VDD0 SYSM XRDE D0 D2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 WDCK XSOE XRAS XWE XCAS CLOK SENS DATA D3 A4 XLAT DVSS D1 A9 A8 A7 A6 A5 XQOK XWRE SCOR SYSM SQSO XSOE SQCK CLOK XEMP XRDE XRST SENS PWMI SCLK DATA XLAT XWIH - 204 - SBSO R4M 120 TEST4 XWRE 31 CXD3048R Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. |
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